In the previous chapters we described algorithms and implementations for arithmetic modules that have the inputs applied all at once (in parallel) and deliver same digit lines. The system is usually clocked so that one digit is applied/deliveredper clock cycle. This serial alternative is the topic of this chapter. We consider thea mixed system in which in which all operands and results are serial, although it is possible to have some inputs and outputs are serial and others parallel. The methods to design these mixed systems can be devised from those for paralleland serial systems.

CHAPTER 9 – Digit-Serial Arithmetic

A N X N bit parallel overlay multiplier architecture is designed for high speed DSP operations. The architecture is based on the vertical and crosswise algorithm of ancient Indian Vedic Mathematics. In the proposed architecture grouping of the bits 4 at a time is done for both the multiplicand and multiplier. Thus the whole multiplication operation is decomposed into 4x4 bit multiplication modules. The 4x4 multiplication modules can be implemented by using any multiplier such as array, booth, wallace or future proposed efficient multiplier. It has been demonstrated that implementing the array and booth multiplier as 4x4 modules in the proposed architecture leads to a considerable improvement in their efficiency. Due to its efficient performance, the overlay architecture is a boon for DSP applications such as multimedia and image processing. In order to test the effect of further decomposition of the bits on the efficiency of the architecture, the 4x4 multiply module are further decomposed into parallel 2x2 multiply modules by grouping two bits at a time for both 4 bit multiplicand and multiplier. The results has shown that decomposition nearly reaches a saturation level in its efficiency at 4x4 decomposition and further decomposition has a not a significant improvement in the architecture efficiency .

High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics

In this paper new multiplier and square architecture is proposed based on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications. It is based on generating all partial products and their sums in one step. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -6. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication and square algorithm implemented in coprocessors. In FPGA implementation it has been found that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier.

A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics.

An FPGA implementation guide for some different types of serial–parallel multiplier structures

An approach is presented to high-performance asynchronous architectures offering significant advantages over conventional clocked systems, without some of the drawbacks normally associated with asynchronous techniques. As the level of integration increases, an asynchronous wavefront array designed using the techniques described will have three important advantages over the equivalent synchronous systolic array: faster throughput (rate at which data are clocked through a system), reduced design complexity, and greater reliability. The benefits and drawbacks of using the asynchronous technique are highlighted using three wavefront arrays: two one-dimensional multipliers, and a two-dimensional sorter. All three can be built using just one basic building block. >

Four state asynchronous architectures

Previous proposals for fast multipliers are discussed, along with a summary of the known theoretical limitations of such designs. Then, a new parallel multiplier with a very simple configuration is suggested. This multiplier operates in time 0(n), where n is the maximum of the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation. It is a logical circuit consisting of 2n modules, each being only slightly more complex than a full adder; instead of three inputs and two outputs, each module has five inputs and three outputs. A logical circuit realization is given for the modules. But perhaps the most significant aspect of this design is the property that the input is required only bit-sequentially and the output is generated bit-sequentially, both at the rate of one bit per time step, least significant bit first. The advantages of such bit-sequential input and output arithmetic units are described.

An 0(n) Parallel Multiplier with Bit-Sequential Input and Output

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An 0(n) Parallel Multiplier with Bit-Sequential Input and Output