We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

/pdf/an-effective-congestion-driven-placement-framework-362g11mcw6.pdf

An effective congestion driven placement framework

In VLSI module placement interconnection behavior becomes increasingly important. Less flexibility first (LFF) principle is derived from human accumulated experience. An interconnection driven VLSI module placement algorithm based on LFF principles is proposed in this paper. We first use quadratic programming to optimize the total wire-length of the placement and then using a deterministic recursive partition rectangle packing algorithm based on LFF principles with consideration of congestion to implement the placement in an estimated fixed die area. Experimental results show efficiency and effectiveness of the proposed method.

Interconnection driven VLSI module placement based on quadratic programming and considering congestion using LFF principles

This paper presents a fast and accurate routing demand estimation called RUDY and its efficient integration in a force-directed quadratic placer to optimize placements for routability. RUDY is based on a rectangular uniform wire density per net and accurately models the routing demand of a circuit as determined by the wire distribution after final routing. Unlike published routing demand estimation, RUDY depends neither on a bin structure nor on a certain routing model to estimate the behavior of a router. Therefore RUDY is independent of the router. Our fast and robust force-directed quadratic placer is based on a generic demand-and-supply model and is guided by the routing demand estimation RUDY to optimize placements for routability. This yields a placer which simultaneously reduces the routing demand in congested regions and increases the routing supply there. Therefore our placer fully utilizes the potential to optimize the routability. This results in the best published routed wirelength of the IBMv2 benchmark suite until now. In detail, our approach outperforms mPL, ROOSTER, and APlace by 9%, 8%, and 5%, respectively. Compared by the CPU times, which ROOSTER needs to place this benchmark, our routability optimization placer is eight times faster

/pdf/fast-and-accurate-routing-demand-estimation-for-efficient-s4q5dpk379.pdf

Fast and accurate routing demand estimation for efficient routability-driven placement

We present a two-stage congestion-driven placement flow. First, during each refinement stage of our multilevel global placement framework, we replace cells based on the wirelength weighted by congestion level to reduce the routing demands of congested regions. Second, after the global placement stage, we allocate appropriate amounts of white space into different regions of the chip according to a congestion map by shifting cut lines in a top-down fashion and apply a detailed placer to legalize the placement and further reduce the half-perimeter wirelength while preserving the distribution of white space. Experimental results show that our placement flow can achieve the best routability with the shortest routed wirelength among publicly available placement tools on IBM v2 benchmarks. Our placer obtains 100% successful routings on 16 IBM v2 benchmarks with shorter routed wirelengths by 3.1% to 24.5% compared to other placement tools. Moreover, our white space allocation approach can significantly improve the routability of placements generated by other placement tools

/pdf/routability-driven-placement-and-white-space-allocation-4n2iqcu5k8.pdf

Routability-Driven Placement and White Space Allocation

In this paper, we present BoxRouter 2.0, a hybrid and robust global router with discussion on its architecture and implementation. As high performance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we propose BoxRouter 2.0 which has strong ability to improve routability and minimize the number of vias with blockages, while minimizing wirelength. BoxRouter 2.0 is improved over [1], but can perform multi-layer routing with 2D global routing and layer assignment. Our 2D global routing is equipped with two ideas: robust negotiation-based A* search for routing stability, and topology-aware wire ripup for flexibility. After 2D global routing, 2D-to-3D mapping is done by the layer assignment which is powered by progressive via/blockage-aware integer linear programming. Experimental results show that BoxRouter 2.0 has better routability with comparable wirelength than other routers on ISPD07 benchmark, and it can complete (no overflow) ISPD98 benchmark for the first time in the literature with the shortest wirelength.

/pdf/boxrouter-2-0-architecture-and-implementation-of-a-hybrid-396zvpz7qr.pdf

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

In this paper, we describe a new congestion-driven placement based on cell inflation. In our approach, we have used the method of probability- estimation to evaluate the routing of nets. We also take use of the strategy of cell inflation to eliminate the routing congestion. Further reduction in congestion is obtained by the scheme of cell moving. We have tested our algorithm on a set of sample circuits from American industry and the results obtained have shown great improvement of routability.

A new congestion-driven placement algorithm based on cell inflation

This paper presents a path-based timing-driven quadratic placement algorithm. The delay of the path acts as the timing constraints. In the global optimization step, it tries to satisfy the timing constraints. In the partition step, it tries to decrease the cut number of critical paths. It has some special skills, such as decreasing the delay on the longest path, and pad assignment, to decrease the delay further. Results show this algorithm can improve the timing behavior more than 20%.

/pdf/a-path-based-timing-driven-quadratic-placement-algorithm-4vuqjye1vw.pdf

A path-based timing-driven quadratic placement algorithm

Placement is the important step in VLSI design. Its speed affects the total speed of design flow, and its result can have a significant effect on subsequent design steps. The quadratic placement method is one of the most successful placement methods. In this paper, we propose a new fast and stable placement algorithm, FaSa. It uses the quadratic placement model and the method of Lagrange multipliers to solve the problem and incremental LU factorization to solve equations. Fasa is much faster than the old algorithms and the total wire length is comparable with other algorithms. FaSa is very stable, and does not depend on any coefficient. We test it with several real circuits. From the results, we see that FaSa is 3 times faster than the previous algorithm.

FaSa: a fast and stable quadratic placement algorithm

Because of the computation complexity of large circuits, the quadratic placement (Q-Place) cannot solve the placement problem fast enough without any preprocessing. In this paper, a method of combining the MFFC clustering and hMETIS partitioning based quadratic placement algorithm is proposed. Experimental results show it can gain good results but consume long running time. In order to cut down the running time, an improved MFFC clustering method (IMFFC) based Q-place algorithm is proposed in this paper. Comparing with the combining clustering and partitioning based method, it is much fast but with a little increase in total wire length.

Combining clustering and partitioning in quadratic placement

Timing and congestion behavior are two important goals in performance-driven standard-cell placement. In this paper, we analyze the relationship between timing and congestion behavior. We introduce a multi-step placement algorithm to optimize the two objects. First, a timing-driven placement step is used to find the global optimal solution. In the second step, the algorithm tries to decrease the maximum congestion while not allowing the timing behavior to deteriorate. We implemented our algorithm and tested it with some real circuits. The results show that the maximum delay decreases more than 30% and the maximum congestion decreases more than 10%.

http://ieeexplore.ieee.org/iel5/7897/21785/01011491.pdf

A standard-cell placement algorithm of optimizing multiple objects

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