Computer vision and image processing algorithms form essential components of many industrial, medical, commercial, and research-related applications. Modern imaging systems provide high resolution images at high frame rates, and are often required to perform complex computations to process image data. However, in many applications rapid processing is required, or it is important to minimise delays for analysis results. In these applications, central processing units (CPUs) are inadequate, as they cannot perform the calculations with sufficient speed. To reduce the computation time, algorithms can be implemented in hardware accelerators such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and graphics processing units (GPUs). However, the selection of a suitable hardware accelerator for a specific application is challenging. Numerous families of DSPs, FPGAs, and GPUs are available, and the technical differences between various hardware accelerators make comparisons difficult. It is also important to know what speed can be achieved using a specific hardware accelerator for a particular algorithm, as the choice of hardware accelerator may depend on both the algorithm and the application. The technical details of hardware accelerators and their performance have been discussed in previous publications. However, there are limitations in many of these presentations, including: inadequate technical details to enable selection of a suitable hardware accelerator; comparisons of hardware accelerators at two different technological levels; and discussion of old technologies. To address these issues, we introduce and discuss important considerations when selecting suitable hardware accelerators for computer vision and image processing tasks, and present a comprehensive review of hardware accelerators. We discuss the practical details of chip architectures, available tools and utilities, development time, and the relative advantages and disadvantages of using DSPs, FPGAs, and GPUs. We provide practical information about state-of-the-art DSPs, FPGAs, and GPUs as well as examples from the literature. Our goal is to enable developers to make a comprehensive comparison between various hardware accelerators, and to select a hardware accelerator that is most suitable for their specific application.

Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms

An ARM-platform and FPGA-based accelerator rather than PC-based system is utilized in this study for completing a real-time FPGA-based human detector. The system presents the advantages of small size, low cost, high computing speed, and being portable and could be built in small cameras for surveillance applications. When background segmentation is introduced, the computing efficiency could reach about 15 fps. Moreover, this study has proven that the reduction on the total detection rate is less than 0.3% while changing HOG algorithm into the presented FPGA hardware implementation.

A Real-Time FPGA Based Human Detector

/pdf/image-boundary-corner-and-edge-detection-past-present-and-4sxht0jrzb.pdf

Image Boundary, Corner, and Edge Detection: Past, Present, and Future

Sea-land segmentation based on edge detection is commonly utilized in ship detection, coastline extraction, and satellite system applications due to its high accuracy and rapid speed. Pixel-level d...

High-Throughput, Resource-Efficient Multi-Dimensional Parallel Architecture for Space-Borne Sea-Land Segmentation

Accelerating image boundary detection by hardware parallelism

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Accelerating image boundary detection by hardware parallelism