2D transition metal chalcogenide (TMDC) materials, such as MoS2, have recently attracted considerable research interest in the context of their use in ultrascaled devices owing to their excellent electronic properties. Microprocessors and neural network circuits based on MoS2 have been developed at a large scale but still do not have an advantage over silicon in terms of their integrated density. In this study, the current structures, contact engineering, and doping methods for 2D TMDC materials for the scaling‐down process and performance optimization are reviewed. Devices are introduced according to a new mechanism to provide the comprehensive prospects for the use of MoS2 beyond the traditional complementary–metal–oxide semiconductor in order to summarize obstacles to the goal of developing high‐density and low‐power integrated circuits (ICs). Finally, prospects for the use of MoS2 in large‐scale ICs from the perspectives of the material, system performance, and application to nonlogic functionalities such as sensor circuits and analogous circuits, are briefly analyzed. The latter issue is along the direction of “more than Moore” research.

The Trend of 2D Transistors toward Integrated Circuits: Scaling Down and New Mechanisms

Among all material systems currently being exploited for tunnel field-effect transistor (TFET) applications, silicon germanium (SiGe) is most likely to be adopted for the future low power very-large-scale integration (VLSI) technologies due to its VLSI-compatibility, mature synthesis techniques, and tunable bandgap. This article demonstrates experimentally the enhancement of the drive current ( ${I}_{ \mathrm{ON}}$ ) and the reduction in the subthreshold swing (SS) of vertical Si p-TFET by inserting a thin layer of boron-doped Si0.8Ge0.2 ( ${E}_{\text {G}}\sim {1}$ eV) between the source and the channel. Owing to the reduction in the tunneling barrier height and the increased lateral electric field, carrier transport across the tunneling junction is significantly enhanced. By improving the material quality, further enhancement in the device performance is observed. Simulation suggests that the proposed structure serves as an effective method to boost the device performance of TFETs.

Vertical P-TFET With a P-Type SiGe Pocket

To overcome scaling issues such as controlling gate leakage, drain induced barrier lowering, higher subthreshold conduction, polysilicon gate depletion, and other short channel effects various engineering proposed. The gate dielectric, metal work function, and device structural engineering enabled the semiconductor industry to make a transition from the conventional planar MOSFET towards a revolutionary 3D tri-gate structure called FinFET. FinFET is one of the fundamental invention in the semiconductor industry, which replaced the planar CMOS technology around 22 nm technology. By following Moore’s law, it accelerated the scaling to 7 nm, but at 5 nm, in the same way, GAAFET replaced FinFET due to technological hurdles. Nanosheet, which is one type of GAAFET are in the recent trend. But researchers are trying to explore the possibilities to continue the miniaturization beyond 3 nm by combining the effect of non-silicon channel material such as Ge, InGaAs, or 2D materials with nanosheet, which will improve the functionality of the device while going down in the technology node. In this survey, an attempt has been made for the structure present till 7 nm process. Also, a few new proposals in research to take the scaling up to 3 nm and beyond are included. The future innovations may put an intercept on the slowing down of Moore’s law, and bring the miniaturization back in the track.

A Journey from Bulk MOSFET to 3 nm and Beyond

RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric

In this present study, junctionless vertical tunnel field-effect transistor (JL-VTFET) with catalytic metals as gate contacts is proposed for gas sensing applications. The vertical double-sided gate architecture provides better gate controllability over conventional TFETs for band-to-band tunneling (BTBT). An architecture for n-channel JL-VTFET with Palladium (Pd) as gate metal is analyzed for Hydrogen sensing, while Cobalt (Co) and Molybdenum (Mo) metals as gate contacts are analyzed for Ammonia sensing. P + pockets are created near the source region by using work function values befitting the aforementioned catalytic metals. Characteristics of the proposed structure are studied considering the electric field, surface potential, and energy bandgap graphs concerning adsorption of gas molecules, using Silvaco ATLAS TCAD simulator. Simulation results of JL-VTFET with 50-nm gate length show good sensitivity calibrations (SIdoff ~ 1.99 × 103, 2.09 × 103 and 6.43 × 102) and high Idon/Idoff ratio (~ 4.3 × 109, ~ 2.01 × 107 and 1.33 × 1012) for Co, Mo and Pd as gate metals, respectively

Design and analysis of double-gate junctionless vertical TFET for gas sensing applications

TFETs are promising candidates for future low-power logic applications because of their potential for outperforming conventional MOSFETs under reduced supply voltage ( ${V} _{\textsf {DD}}$ ). Among all material systems currently being explored, group IV semiconductor SiGe holds the most potential due to its very large scale integration (VLSI) compatibility, mature synthesis techniques, and tunable bandgap, making it more likely to be adopted for future VLSI technologies. It has been shown experimentally that the on-state current ( ${I} _{\textsf {on}}$ ) of SiGe TFETs improves significantly with the increasing Ge content. However, increasing the Ge content leads to excessive leakage in the off-state and poses a challenge to the pseudomorphic growth of SiGe. In this paper, the concept of Ge-pocket TFET with a counter-doped pocket is proposed. By confining Ge to the pocket region, the proposed structure circumvents those problems. Both the steep subthreshold swing and high ${I} _{\textsf {on}}$ can be achieved. The proposed TFET also demonstrates excellent scalability in terms of physical gate length ( ${L} _{\textsf {gate}}$ ) and ${V} _{\textsf {DD}}$ , which makes it a promising replacement of conventional MOSFETs for low-power logic applications.

Optimization and Scaling of Ge-Pocket TFET

Ternary PtPdCo mesoporous nanospheres with superior electrocatalytic performance towards methanol oxidation reaction

A TCAD-based study on the parasitic resistance (R parasitics ) of 10nm FinFET is performed. A total parasitic resistance of 1490Q/Fin is extracted using calibrated physical models, and the components of the R parasitics are evaluated. It is observed that by introducing wraparound contact and highly doped source/drain, contact resistance (R contact ) of 10nm FinFET is well minimized and current crowding in the fin is suppressed. It is also found that the resistance of the lightly doped spacer region (R spacer ) constitutes more than 50% of total R parasitics and can be optimized by introducing highly doped segments. With the optimized doping profile in the spacer, drain current (Id) and intrinsic gain (Av) can be improved by 11% and 16%, respectively. In the case for 7nm-node FinFET, it was concluded that further R contact reduction is also needed to optimize its performance.

Parasitic resistance modeling and optimization for 10nm-node FinFET

Study on the Effect of Acetate Ions on the Sealing Treatment for Anodic Oxide Film of 6063 Aluminum Alloy

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