This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs) This approach utilizes calculations of surface potential ( ${\psi _s}$ ) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental $I - V$ characteristics from irradiated devices The modeling approach is suitable for simulating TID and aging effects in advanced MOS devices and ICs, and is compatible with modern MOSFET compact modeling techniques A circuit-level demonstration is given for TID and aging effects in SRAM cells

Compact Modeling of Total Ionizing Dose and Aging Effects in MOS Technologies

The surface-potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region As a result, MM20 extends its application range from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V In this paper, the new dc model of MM20, including quasi-saturation, is presented The addition of velocity saturation in the drift region ensures the current to be controlled by either the channel region or the drift region A comparison with dc measurements on a 60-V LDMOS device shows that the new model provides an accurate description in all regimes of operation, ranging from subthreshold to superthreshold, in both the linear and saturation regime Thus, owing to the inclusion of quasi-saturation also the regime of high-gate and high-drain bias conditions for high-voltage LDMOS devices is accurately described

Compact modeling of high-voltage LDMOS devices including quasi-saturation

This paper reviews the industry-standard surface-potential-based compact model HiSIM_HV for high-voltage MOSFETs, as, e.g., the lateral double-diffused MOS transistor, and introduces important improvements implemented in the second-generation model versions (HiSIM_HV2), for which open source code has been released since October 2011. HiSIM_HV solves the Poisson equation consistently within the intrinsic MOSFET, i.e., the gate-drift overlap region and the drain-side part of the drift region. Excess carrier concentrations in the drift region are accurately considered together with the velocity saturation effect. These modeling concepts enable a scalable compact model formulation with only one internal node. Fulfillment of the current continuity between MOSFET and drift parts is required for determining the internal node potential. An important enhancement implemented in the HiSIM_HV2 models is a physically accurate compact drift region resistance model, which captures the effects of the structure-dependent 2-D current flows in overlap and drift regions with their complicated bias dependence. Furthermore, compact modeling of gate overlap capacitance, leakage currents due to, e.g., impact ionization, self-heating, noise, and symmetry properties (smooth derivatives at zero drain-source voltage) have been substantially improved.

The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs

This paper introduces a scalable compact model of lateral double-diffused MOS (LDMOS) transistors. The new model, i.e., the Surface-Potential-based High-Voltage MOS (SP-HV), is constructed from a surface-potential-based bulk MOS field-effect transistor model, i.e., PSP, and a nonlinear resistor model, i.e., R3. Extensions are made to both PSP and R3 for improved modeling of LDMOS devices, and one internal node is introduced to connect the two component models. The new model is validated by comparison to technology computer-aided design (TCAD) simulations and experimental data. Quasi-saturation, self-heating, impact ionization current in the drift region, and complex behavior of transcapacitances are accurately modeled by SP-HV.

SP-HV: A Scalable Surface-Potential-Based Compact Model for LDMOS Transistors

The radiation response of advanced non-planar multiple gate field effect transistors (MuGFETs) has been shown to have a strong dependence on fin width (W). The incorporation of total ionizing dose (TID) effects into a physics-based surface-potential compact model allows for the effects of radiation-induced degradation in MuGFET devices to be modeled in circuit simulators, e.g., SPICE. A set of extracted parameters are used in conjunction with closed-form expressions for the surface potential, thereby enabling accurate modeling of the radiation-response and its dependence on W . Total ionizing dose (TID) experiments and two-dimensional (2D) TCAD simulations are used to validate the compact modeling approach presented in this paper.

Modeling of Ionizing Radiation-Induced Degradation in Multiple Gate Field Effect Transistors

This paper presents a compact model of impact ionization currents in lateral double-diffused MOS (LDMOS) transistors. Depending on bias conditions, impact ionization in LDMOS transistors primarily occurs either in the intrinsic MOSFET or in the drift region, leading to a “double-hump” substrate current behavior and enhanced drain current when both VG and VD are high. Impact ionization in the drift region also causes the “expansion” effect, which is modeled by making the drift region resistance a function of the impact ionization current in the same region. The new model is verified by comparison with TCAD simulations and experimental data. The interaction between the expansion effect and self-heating is also accurately captured by the model.

Compact Model of Impact Ionization in LDMOS Transistors

We present a complete surface-potential-based compact model of dynamically depleted (DD) SOI MOSFETs. The surface potential equation of DD-SOI MOSFETs was reconditioned to avoid the unphysical behaviors near the flat-band voltage. In order to capture the dynamic depletion effect, the coupling equation for the front and back surface potentials was reformulated to include the back gate effect, which is not available in other surface-potential-based DD-SOI compact models. The new formulation of surface potential and coupling equations was verified by comparing with numerical computations combining the Pao–Sah double integral based formulation and the exact coupling equation. To obtain explicit expressions for the terminal charges and drain current, a new symmetric linearization method has been proposed. The complete model, PSP-SOI DD is implemented in the context of the PSP and PSP-SOI PD models and includes all the secondary effects, floating body simulation capability, etc. The new model has been extensively verified with 2D TCAD simulation results and accurately captures the manifestation of the dynamic depletion effect observed in the device characteristics.

Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

We report the compact modeling of junction current in dynamically depleted silicon-on-insulator (SOI) MOSFETs. The body-to-source built-in barrier lowering is obtained from the coupled surface potential equations which serve as the basis of surface-potential-based SOI MOSFET models. This barrier lowering is then incorporated into the advanced junction model to enable the unification of junction current in partially depleted and fully depleted SOI MOSFET models. Compared with 2-D TCAD simulations, the characteristics of body-to-source/drain junction current in dynamically depleted SOI MOSFETs are faithfully reproduced by the new approach.

Compact Modeling of Junction Current in Dynamically Depleted SOI MOSFETs

Surface-potential-based models, which represent the mainstream ap- proach to compact modeling of bulk MOSFETs, are now in the process of being applied to SOI devices. In this chapter we discuss two advanced SOI models—PSP- SOI-PD for partially depleted devices and PSP-SOI-DD including the dynamic de- pletion effects. Both models are based on the popular PSP model of bulk MOSFETs. The theoretical foundation of all PSP-family models is the symmetric linearization method that allows one to raise the physical contents of the compact model with- out prohibitive increase in its computational complexity. In addition to the physics- based structure of the new models inherited from bulk PSP, they account for phe- nomena specific to SOI devices (e.g. floating body, and valence band tunneling cur- rent) and include a detailed description of parasitic effects. We discuss both the theoretical developments and verification of the model against test data and TCAD simulations with particular emphasis on the interplay between the model structure and its simulation capabilities.

/pdf/psp-soi-a-surface-potential-based-compact-model-of-soi-1fjpolvr3s.pdf

PSP-SOI: A Surface-Potential-Based Compact Model of SOI MOSFETs

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