Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV.

Hybrid bonding with through substrate via (tsv)

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region

Conductive barrier direct hybrid bonding

A semiconductor device includes a first laminated body and a second laminated body. The first laminated body includes sequentially a first element, a first wiring layer, and a first connection layer that includes a first junction electrode, on a main surface of a first substrate. The second laminated body includes sequentially a second element, a second wiring layer, and a second connection layer that includes a second junction electrode, on a main surface of a semiconductor substrate. The first laminated body and the second laminated body are bonded by directly bonding the first junction electrode and the second junction electrode with the two junction electrodes facing each other. A space region is formed at a part of a junction interface between the first laminated body and the second laminated body.

Semiconductor device and method for manufacturing same

Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.

Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure

A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Seal ring structures and methods of forming same

A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.

Substrate bonding with diffusion barrier structures

A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together. The bonding process includes simultaneously thermally treating at least one of the wafers in situ by individually adjusting the temperature of one or more thermal actuators in the array in accordance with the wafer temperature profile model and the local heat flux model to induce thermal expansion over a surface area corresponding to the dimensions of each adjusted thermal actuator.

Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process

The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.

Handler wafer removal by use of sacrificial inert layer

A novel hybrid bonding process has been developed that achieved a successful copper/SiO
 2
 heterogeneous bonding.

Copper-to-dielectric heterogeneous bonding for 3D integration

A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.

Wafer bonding using boron and nitrogen based bonding stack

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