Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.

/pdf/fixed-outline-floorplanning-enabling-hierarchical-design-23xngcvy40.pdf

Fixed-outline floorplanning: enabling hierarchical design

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

A system and method for designing ICs, including the steps of: analyzing and optimizing a target IC design based on design-specific objectives; partitioning the optimized target IC design into pre-defined standard-cells from one or more libraries and creating design-specific cells specifically having unique functionality and characteristics not found amongst the standard-cells; identifying and determining a minimal subset of the standard-cells and design-specific cells, the interconnection of which represents the target IC design; generating the necessary views, including layout and characterizing of the design-specific cells included in a unique, minimal subset, wherein the IC design is subject to objectives and constraints of the target IC.

Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks

Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. The forces are optionally selectively modulated as a function of simulation time. The placements of the devices are compatible with various design flows, such as standard cell, structured array, gate array, and field-programmable gate array.

Methods and systems for placement

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

Methods for defining contact grid in dynamic array architecture

In computer-aided electronic design automation software, a placement system biases clustering of cells according to their hierarchical design while optimizing placement for controlling die size and total wire length. The placement system also provides for slack distribution, row improvement and randomization during partitioning. Floor plans based on trial placement and placement guiding blocks are also described.

Design hierarchy-based placement

Disclosed herein is a method (60) for dividing an integrated circuit (IC) design (45) into several circuit partitions (41, 42, 43, 44), each including one or more circuit modules, and then separately carrying out placement and routing for each circuit partition, with each partition being implemented within a separate area of an IC substrate. The method (60) initially generates a whole-chip trial placement that tends to cluster cells of each circuit module together. An IC substrate floor with the size, shape and relative position of each partition being determined by size, shape and relative position of areas of the substrate occupied by those modules in the trial floor plan. A trial routing is also performed to information on which to base a pin assignment plan for each module. A detailed placement and routing process is then independently performed for each partition, with placement and routing of cells within each partition constrained by the floor plan and pin assignment plan.

Integrated circuit partitioning, placement and routing system

An integrated circuit (IC) layout process is organized into two phases. During the Phase 1 of the process, a preliminary placement plan is generated fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is also generated establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets various signal path timing, signal integrity, and power distribution and other constraints. Thereafter, at the start of Phase 2 of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the exact routes to be followed by all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.

IC layout system having separate trial and detailed routing phases

A design methodology for the implementation of multi-million gate system-on-chip designs is described. The new methodology is based on the creation of a silicon virtual prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'cockpit' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The silicon virtual prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.

/pdf/silicon-virtual-prototyping-the-new-cockpit-for-nanometer-5cdgvke6m4.pdf

Silicon virtual prototyping: the new cockpit for nanometer chip design [SoC]

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Design hierarchy-based placement

Integrated circuit partitioning, placement and routing system

IC layout system having separate trial and detailed routing phases

Silicon virtual prototyping: the new cockpit for nanometer chip design [SoC]