Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling

https://iopscience.iop.org/article/10.1088/0268-1242/22/1/S42/pdf

Enhancing CMOS Transistor Performance Using Lattice-Mismatched Materials in Source/Drain Regions

Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 °C. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.

https://ir.nctu.edu.tw:443/bitstream/11536/24017/1/000332040700001.pdf

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.

Low defect si:c layer with retrograde carbon profile

We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions followed by selective epitaxy of SiCP was adopted. High in situ doping contributes to low series resistance to channel resistance ratio and is important for reaping the benefits of strain. Substitutional carbon concentration was varied, showing enhanced drive current with increased for comparable off-state leakage, series resistance, and control of short-channel effects. A record high carbon substitutional concentration of 2.1% was achieved. Use of heavily doped silicon-carbon stressor with large lattice mismatch with respect to Si and placed in close proximity to the channel region in the SDE regions is expected to be important for strain engineering in nanoscale N-FETs.

Silicon–Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

The semiconductor industry has entered a new revolution where connectivity, applications, and an overall pervasive market drives the need for increased circuit density, improved performance, and a decrease in power dissipation. These issues are the backbone for some of the latest silicon technology advancements, including the integration of stress-enabled transistors and advanced silicon-on-insulator substrates. Future advancements may include multiple gated devices, high- gate oxides, and band-gap-tailored devices. This paper will review some of the early complementary metal-oxide-semiconductor transistor reliability issues and solutions that have allowed this industry to flourish over the last 25 years. A discussion on how these past issues and new advances affect power versus performance is the framework and motivation of this paper.

MOS Technology Drivers

A novel n-channel strained SOI transistor featuring silicon-carbon (SiC) source/drain (S/D) regions and tensile stress silicon nitride (SiN) liner is demonstrated for the first time. Drive current IDsat enhancement contributed by the dual stressors is found to be additive and a significant increase in IDsat of 55% is observed at a gate length LG of 50 nm. In addition, we report the dependence of drive current on channel orientation, with highest I Dsat observed for strained n-MOSFETs with the |010| channel direction. A study of the carrier transport characteristics indicate reduced channel back-scattering and enhanced carrier injection velocity due to the strain effects

50 nm Silicon-On-Insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source/Drain Regions and Tensile Stress Silicon Nitride Liner

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50 nm Silicon-On-Insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source/Drain Regions and Tensile Stress Silicon Nitride Liner