In today's nanometric VLSI designs achieving both power and performance targets is the top most priority for design closure Globally asynchronous locally synchronous (GALS) architectures can offer less dynamic power and improved performance due to absence of global clock In GALS SoC architectures each synchronous blocks runs on their local clocks Synchronous blocks communicate with each other by pausing their local clocks using an asynchronous interface which is implemented using various handshake protocols However any synchronous block which has to wait long time for data from another block need to be in idle state and as a result will dissipate significant leakage power in nanometric designs Power gating is an effective technique to reduce leakage power of an idle circuit in synchronous designs However implementing such power gating interface in GALS architecture is a challenge in the absence of clock Thus to reduce the leakage power in ideal blocks which are waiting for the data, a new GALS wrapper interface was proposed which can generate power gating sequence To corroborate the proposed interface a GALS 8051 was implemented using Synopsys SAED 90 nm libraries The power gating sequence of 8051 asynchronous wrappers are used to gate the power of Random Access Memory (RAM) block while Arithmetic Logic Unit (ALU) block is busy in doing arithmetic operations The experimental results show a 30% reduction in leakage power of RAM block due to power gating

A power gating GALS interface implementation

Complex SoC imply the seamless integration of numerous IPs performing different functions and operating at different clock frequencies The integration of several heterogeneous components into a single system gives rise to new challenges Major issue includes controlling the clock frequencies of the different modules As chips become faster and larger, designers face significant challenges including global clock distribution and power dissipation In-order to achieve global synchronization with high performance and low power conception globally asynchronous locally synchronous (GALS) method is used In GALS, local modules can operate with their own clock and the entire module is communicating asynchronously In this paper we implemented a low power GALS interface with stretchable clocking scheme in verilog HDL and compare the dynamic power of the interface with and without stretchable clocking with Synopsys Design Compiler

/pdf/low-power-gals-interface-implementation-with-stretchable-37ooucmo7r.pdf

Low Power GALS Interface Implementation with Stretchable Clocking Scheme

With the improving evolution in VLSI technology most of the digital circuits are becoming SOCs However most of the SOC systems are synchronous designs and the issues like clock skew, power consumption and EMI are related to clock network Asynchronous circuits can offer benefits like reduced power and improved performance However implementing whole design with asynchronous design style is a challenge due to lack of CAD tools The GALS (Globally-Asynchronous Locally-Synchronous) design methods brings compromise between synchronous and asynchronous design styles by separating each synchronous blocks in SoC with asynchronous interface Each synchronous block in SoC can perform operation with its own local clock The data communication among synchronous blocks can be achieved via handshaking signals after pausing the local clocks Though these GALS system architectures ensures less dynamic power through clock less asynchronous interface the leakage power contribution to total power equation is still a challenge in deep submicron technologies Power gating is most effective technique for synchronous design to address leakage power In this paper an asynchronous power gating sequence generation is proposed for GALS synchronous blocks which has to wait long time for data To corroborate the proposed technique a synthesis flow is proposed to implement asynchronous 8051 micro controller The implementation was done using Synopsys SAED 90 nm libraries and the experimental results shows 30% leakage power reduction for power gating blocks

Synthesizing power gating sequence in pausible clock based GALS designs

The design of System-on-Chip systems using synchronous circuits involves complex clock distribution strategies, which envisage challenges for designers to integrate large-scale systems. Globally Asynchronous Locally Synchronous architectures containing asynchronous port controllers encapsulated in the self-timed wrapper have been adopted in this work. These port controllers communicate through Asynchronous Finite State Machines defined by Signal Transition Graphs are implemented adopting the C element. This GALS architecture implemented for the point-to-point interface can also be modified for the multipoint interface. The proposed methodology uses a two-phase handshake protocol to communicate between two Locally Synchronous modules as it has fewer signal transitions, which, in turn, reduces latency. In this paper, the Queue Direct Memory Access subsystem is implemented using the Vivado simulator on UltraScale+™ device at a maximum frequency of 257.4MHz, and various parameters are reported. A comparison shows that the proposed wrapper has improved latency time of 53%, with a reduction in power dissipated by 27% and an increase in gate count by 13%. 

Asynchronous Wrapper-Based Low-Power GALS Structural QDMA

With the VLSI technology improving rapidly, SoC has been becoming the most important VLSI application. However, clock distribution and low power have already become the two most important issues in SoC design. In addition, it's also a very important issue to integrate IPs that can perform operations correctly with different clocks. Asynchronous circuits may resolve these problems by removing the “clock” signal. But it's too hard to implement the whole circuits with asynchronous circuit. The GALS (Globally-Asynchronous Locally-Synchronous) design methodology can balance this problem via separating each synchronous design with asynchronous interface. Thus, each part of the circuit can perform operations with its own clock. The communication between different parts of the circuit can be achieved via asynchronous channels. The GALS provides a reliable communication between different modules. However, the latency of GALS interface may cause performance degradation seriously. Thus how to reduce the latency of GALS interface is significant. In this paper, we implemented a small and simple stretchable-clock based GALS wrapper with low-latency in Verilog HDL and synthesized the design with TSMC 0.13µm cell library. We also showed that the wrapper can operate correctly with modules which operate with great different clock frequencies. In addition, we also recommend adding FIFO storage element on the transmission path.

A low-latency GALS interface implementation

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Wei-Che Chen

Author Tools

Chat about Author

Papers

A low-latency GALS interface implementation