An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Parallel encoding for non-binary linear block code

A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.

Parallelization of error analysis circuitry for reduced power consumption

A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.

Error locator polynomial decoder and method

The invention relates to the communication technology and discloses an RS (reed Solomon) decoding method and device thereof in the communication system By serial decomposition calculation of common parallel iBM algorithm, hardware resource required for solving key equations is greatly reduced and path delay is reduced under the condition of no influence on continuous decoding Also, by combining and optimizing Chien search and Forney algorithm process, that is, odd-even terms in error position polynomial terminals and error value polynomial terms are split, and control logic and repeated calculation is reduced Therefore, consumption of the hardware resource is only 1/2 to 1/3 of that of the common iBM algorithm, the maximum clock frequency and effective data bandwidth are improved by about 30%, high-speed channel error technology can be applied on a low-density chip, and cost is reduced

RS (reed Solomon) decoding method and device thereof in communication system

The invention relates to a variable-order pipeline serial multiply-accumulator comprising a group of multipliers, three groups of accumulators and corresponding control circuits. The group of multipliers is used for multiplying of two channels of input data and outputting multiplying results. The first group of the three groups of accumulators is used for accumulating the multiplying results, the other two of the three groups of accumulators are used for accumulating pipeline results of the first group of accumulators after the accumulating process of the first group of accumulators, and thus, the first group of accumulators can continue to process data of the next stage. The corresponding control circuits are used for adding extra control signals and control logics and eliminating the head-tail zero padding process of algorithms. The variable-order pipeline serial multiply-accumulator has the advantage that, in application, the head-tail zero padding process of the algorithms and redundant multiplying and accumulating caused by the head-tail zero padding process can be omitted during computing, and accordingly performance index approaching the theoretical estimation can be acquired.

Variable-order pipeline serial multiply-accumulator

The invention discloses an implementation method of a Reed-Solomon decoder. The Reed-Solomon decoder realizes solving on an error location polynomial and an error value polynomial by a controller, an arithmetic device and four shifting registers, and can decode a plurality of symbols of a Reed-Solomon code, thus achieving small and fixed delay time for decoding and regular structure.

Implementation method of Reed-Solomon decoder

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Implementation method of Reed-Solomon decoder