A binary neural network accumulator circuit based on an analogue delay chain, which belongs to the technical field of basic electronic circuits. The binary neural network accumulator circuit comprises a delay chain module with two delay chains and a pulse generation circuit, wherein the analogue delay chain is composed of multiple analogue delay cells connected in series, and the analogue delay cells use six MOS transistors and determine "0" and "1" by means of the size of delay. An analogue calculation method is used to replace cumulative calculation in a traditional digital circuit design. Moreover, the accumulator structure can work stably within a wide voltage, and circuit implementation is simple, thereby effectively reducing the power consumption of binary neural network accumulator calculation, and greatly improving the energy efficiency of a neural network circuit.

Binary neural network accumulator circuit based on analogue delay chain

The invention provides a memory operation circuit and a chip structure. The memory operation circuit comprises a read word line and a read bit line; a storage unit provided with a main storage node and an auxiliary storage node which are complementary; a pull-down switch, wherein the control end of the pull-down switch is connected with the auxiliary storage node or the main storage node, and theoutput end of the pull-down switch is grounded; a read control switch, wherein the control end of the read control switch is connected with the read word line, the input end of the read control switchis connected with the read bit line, and the output end of the read control switch is connected with the input end of the pull-down switch; and at least one pull-down unit, wherein the input end of each pull-down unit is connected with the reading bit line, the output end of each pull-down unit is grounded, at least one control signal is accessed to the control end of each pull-down unit, and each pull-down unit is used for being conducted when each accessed control signal is at a high level. According to the embodiment of the invention, before the logic value stored in the storage unit is read out, OR operation can be carried out on the logic value and other logic values or logic relational expressions in the memory, so that the calculation efficiency can be improved.

Memory operation circuit and chip structure

The invention discloses an in-memory computing circuit suitable for a full-connection binary neural network which belongs to the technical field of basic electronic circuits. The circuit comprises aninput latch circuit, a counting addressing module, an address selector, a decoding and word line driving circuit, a storage array, a pre-charging circuit, a writing bit line driving circuit, a copyingbit line array unit, a sequential control circuit, a sensitive amplifier, an NAND gate array, an output latch circuit and an analog delay chain. Parallel XNOR operation is executed on an SRAM bit line, and accumulation, activation and other operations are executed by a delay chain in a time domain. Because partial calculation is completed while data is read, and the delay chain with small area occupation can be integrated with the SRAM, the energy consumption of the memory access process is reduced, the throughput of the system is also improved by multi-column parallel calculation, and compared with an accelerator adopting a Von Noemann architecture, the overall power consumption of the network can be remarkably reduced, and the energy efficiency is improved.

In-memory computing circuit suitable for full-connection binary neural network

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In-memory computing circuit suitable for full-connection binary neural network