The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.

Integrated circuit chip device and related product

The invention discloses a low-bit wide convolution neural network reconfigurable computing unit. The unit comprises a plurality of reconfigurable shift accumulator modules, a multiplexer and a quantization processing module, wherein the reconfigurable shift accumulator modules include a controller, a first register, a second register, a third register and a shift accumulator. The controller, the first register, the second register, the third register and the shift accumulator are constructed by means of network discreteness, and the controller is used for judging whether the fixed-point numberdata and exponential weight of a current cycle are zero or not. Once the fixed-point number data and the exponential weight of the current cycle are detected to be zero, the third register is controlled to output shift accumulation data of the current cycle according to a first trigger signal transmitted by the first register and a second trigger signal transmitted by the second register. Throughadoption of the low-bit wide convolution neural network reconfigurable computing unit, 4-bit and 8-bit flexible fixed-point multiplication and accumulation operations can be realized; the shift accumulation operation rate can be increased; and the memory and power consumption occupied by the operations are lowered.

Low-bit wide convolution neural network reconfigurable computing unit

The invention relates to a neural network accelerator for facing a multi-variant LSTM. The neural network accelerator comprises the components of a storage unit which is used for storing neuron data and weight data of the LSTM and the variant network and outputting; a matrix multiplication unit which is used for receiving data from the storage unit, executing a vector multiplying and accumulatingoperation on the received data and outputting an operation result; a multifunctional operating unit which is used for receiving data from a vector multiplication operation unit, performs a specific operation which corresponds with the LSTM or the variant network for aiming at the received data and outputs an operation result; an activating unit which is used for receiving data from the multifunctional operating unit and the storage unit, performs an activation operation for aiming at the received data and outputs an activation result; and a vector parallel multiplying and adding unit which isused for receiving data from the activating unit and the storage unit and performing a multiplying operation and an adding operation for aiming at the received data.

Neural network accelerator for facing multi-variant LSTM and data processing method thereof

The invention relates to a neural network accelerator. The neural network accelerator comprises a storage unit for storing neuron data and weight data of an LSTM network and outputting the data, a vector multiplying and accumulating matrix unit used for receiving the data from the storage unit, performing vector multiplying and accumulating operations for the received data and outputting operationresults, an addition unit used for receiving the data from the vector multiplying and accumulating matrix unit and performing an offset addition operation for the received data, an activation unit used for receiving the data from the multifunctional operation unit and/or the storage unit, performing an activation operation and outputting an activation result for the received data, and a vector parallel multiplying and accumulating unit used for receiving the data from the activation unit and/or the storage unit and performing multiplying and accumulating operations on the received data. All the modules are connected end to end to form an assembly line working mechanism to carry out data processing together with input vectors by taking weighted row vectors as a unit.

Neural network accelerator and data processing method

The invention belongs to the technical field of integrated circuit design, and particularly relates to a hardware implementation circuit for a gating unit acceleration operation in an LSTM (Long Short-Term Memory). The LSTM comprises three gating units, including an input gate, a forgotten gate and an output gate, and the hardware circuit structure of each gating unit of the LSTM is the same and consists of four parts, including a data transmission module, an input layer multiply-accumulation module used for finishing matrix vector multiplication, a hidden layer multiply-accumulation module and a nonlinear activation function module. The circuit transmits data required by the gating unit to an arithmetic unit through the data transmission module, the matrix vector multiplication is finished through the input layer multiply-accumulation module and the hidden layer multiply-accumulation module, and finally, the operation of the integral gating unit in the LSTM can be finished through thenonlinear activation function module. By use of the circuit, the data can be reused and be parallel in the multiply-accumulation modules, a piecewise linear approximation method is adopted in the nonlinear activation function module to reduce hardware resource consumption and circuit time delays, circuit complexity is greatly reduced, and circuit performance is improved.

Hardware implementation circuit for gating unit acceleration operation in LSTM (Long Short-Term Memory)

The invention discloses a multi-computing-unit coarse-grained reconfigurable system and method for a recurrent neural network LSTM (long short-term memory). The system comprises multi-matrix-product bias and calculation arrays, activation fitting calculation arrays and vector quantity calculation arrays. The multi-matrix-product bias and calculation arrays are used for realizing calculation and accumulation operation of multiple matrix vector products in the recurrent neural network and perform addition bias calculation under control of control signals, and output values are outputted through corresponding output cache units. The activation fitting calculation arrays are used for realizing a piecewise linear fitting calculation function of activation functions in the recurrent neural network LSTM, activation fitting calculation units are controlled by the control signals to perform corresponding activation function piecewise linear fitting calculation when input values enter input cache units, and output values are outputted through corresponding output cache units. The vector quantity calculation arrays are used for realizing dimension-based vector multiplication and vector addition calculation, and after multiplication units finish calculation, data are transmitted to vector addition units or directly outputted under control of the control signals. Parallelism degree, calculation speed and array utilization rate of the reconfigurable system are increased.

Multi-computing-unit coarse-grained reconfigurable system and method for recurrent neural network

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Multi-computing-unit coarse-grained reconfigurable system and method for recurrent neural network