Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review article, different technologies for Multiple-valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies, and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic.

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Investigation of Multiple-valued Logic Technologies for Beyond-binary Era

Neuromorphic computing hardware has undergone a rapid development and progress in the past few years. One of the key components in neuromorphic computing systems is the neural encoder which transforms sensory information into spike trains. In this paper, both rate encoding and temporal encoding schemes are discussed. Two novel temporal encoding schemes, parallel and iteration, are presented. The power consumption of the encoder has been significantly reduced by combing the iteration encoding and low sampling rate in advanced complementary metal-oxide semiconductor (CMOS) nano-technology. Both the simulation and measurement results show the accuracy and efficiency of the proposed encoding circuits. The proposed iteration encoder has immediate applicability as a general purpose input encoder for a reservoir computing system.

Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems

Von Neumann bottleneck, which refers to the limited throughput between the CPU and memory, has already become a major factor hindering the technical advances of computing systems. In recent years, neuromorphic systems have started to gain the increasing attentions as compact and energy-efficient computing platforms. As one of the most crucial components in the neuromorphic computing systems, neural encoder transforms the stimulus (input signals) into spike trains. In this paper, we adapt the temporal encoding scheme of interspike intervals (ISIs) and present an analog temporal neural encoder with its verification and recovery schemes. The proposed neural encoder allows efficient mapping of signal amplitude information into a spike-time sequence that represents the input data and offers perfect recovery for band-limited stimuli. With the novel iterative structure, the number of spikes increases exponentially with the number of neurons. From the measurements obtained from the fabricated neural encoder chip, our temporal encoder with ISI encoding is proved to be robust and error tolerant.

Interspike-Interval-Based Analog Spike-Time-Dependent Encoder for Neuromorphic Processors

Hardware Trojans have emerged as an insidious problem in the global electronics supply chain. This paper surveys how VLSI testing principles can be adapted to protect ICs against hardware trojans.

/pdf/protection-against-hardware-trojans-with-logic-testing-4okvycmwkh.pdf

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead

A fast channel prediction scheme is proposed for Ricean fading scenarios. By employing an echo state network (ESN), the scheme is able to obtain smaller prediction error than previous designs. Simulation results show that the ESN prediction method has lower normalized mean squared error than the traditional autoregressive, discrete wavelet transform, and support vector machine prediction approaches. The symbol error rate gap between the perfect and predicted channel state information is small.

Echo State Network for Fast Channel Prediction in Ricean Fading Scenarios

Neuromorphic computing is a novel paradigm that inspired from the dynamic behavior of the biological brain. The encoding capability plays a vital role in information processing, especially for neural network based systems. In this paper, a compact, low power, and robust spiking-time-dependent encoder is designed with an accommodative Leaky Integrate and Fire (LIF) model based neuron cluster and a chaotic circuit with ring oscillators. Novel and fundamental methodologies, which represent data by using spike timing dependent encoding, has been developed. The information in signal amplitude has been mapped into a spike time sequence efficiently by time encoding, which represents the input data and offers perfect recovery for band limited stimuli. Time dependent temporal scales have been adopted to pattern the neural activities across multiple timescales and encode the sensory information. Furthermore, chaotic circuit based Pseudorandom Time Series Generator (PTSG) is designed to generate sampling clock. High resolution is provided with chaotic based sampling in the proposed encoding circuit. Detailed post layout simulation results and analysis of the designed circuit are presented.

Neuromorphic encoding system design with chaos based CMOS analog neuron

Truly polymorphic circuits, whose functionality/circuit behavior can be altered using a control variable, can provide tremendous benefits in multi-functional system design and resource sharing. For secure and fault tolerant hardware designs these can be crucial as well. Polymorphic circuits work in literature so far either rely on environmental parameters such as temperature, variation etc. or on special devices such as ambipolar FET, configurable magnetic devices, etc., that often result in inefficiencies in performance and/or realization. In this paper, we introduce a novel polymorphic circuit design approach where deterministic interference between nano-metal lines is leveraged for logic computing and configuration. For computing, the proposed approach relies on nano-metal lines, their interference and commonly used FETs. For polymorphism, it requires only an extra metal line that carries the control signal. In this paper, we show a wide range of crosstalk polymorphic logic gates and their evaluation results. We also show an example of a large circuit that performs both the functionalities of multiplier and sorter depending on the configuration signal. A comparison is made with respect to other existing approaches in literature, and transistor count is benchmarked. For crosstalk-polymorphic circuits, the transistor count reduction range from 25% to 83% with respect to various other approaches. For example, polymorphic AOI21-OA21 cell show 83%, 85% and 50% transistor count reduction, and Multiplier-Sorter circuit show 40%, 36% and 28% transistor count reduction with respect to CMOS, genetically evolved, and ambipolar transistor based polymorphic circuits, respectively.

Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits

Offshore fabrication, assembling and packaging challenge chip security, as original chip designs may be tampered by malicious insertions, known as hardware Trojans (HTs). HT detection is imperative to guarantee the chip performance and safety. Existing HT detection methods have limited capability to detect small-scale HTs and are further challenged by the increased process variation. To increase HT detection sensitivity and reduce chip authorization time, we propose to exploit the inherent feature of differential cascade voltage switch logic (DCVSL) to detect HTs at runtime. In normal operation, a system implemented with DCVSL always produces complementary logic values in internal nets and final outputs. Noncomplementary values on inputs and internal nets in DCVSL systems potentially result in abnormal power behavior and even system failures. By examining special power characteristics of DCVSL systems upon HT insertion, we can detect HTs, even if the HT size is small. Simulation results show that the proposed method achieves up to 100% HT detection rate. The evaluation on ISCAS benchmark circuits shows that the proposed method obtains a HT detection rate in the range of 66% to 98%.

/pdf/efficient-hardware-trojan-detection-with-differential-55vprnqi86.pdf

Efficient hardware trojan detection with differential cascade voltage switch logic

Reservoir Computing (RC) is a recent neurologically inspired concept for processing time dependent data that lends itself particularly well to hardware implementation by using the device physics to conduct information processing. In this paper, we apply RC to channel estimation in Orthogonal Frequency Division Multiplexing (OFDM) systems. Due to the multipath propagation environment between a transmitter and receiver, the received signal undergoes attenuation, time delay and phase shift. For mitigating these random effects and decoding the transmitted signal at the receiver, accurate channel estimation is vital. Statistical approaches for channel estimation assume that accurate channel information is available at the receiver. However, the time-variance of the channel complicates the channel estimation process by making the current estimation outdated. Recurrent Neural Networks (RNNs), which are analogous to the functioning of the human brain, are therefore utilized for channel prediction. Training algorithms for RNNs are categorized as gradient-descent methods, which often results in high computational complexity and leads to non-convergence due to the presence of bifurcations. In this paper, an Echo State Network (ESN), which is a class of RC approach, has been used for training a RNN to estimate the channel state information. Using this approach, the training and hence, the implementation complexity is significantly reduced. Simulation results show significant improvement in channel estimation accuracy for the proposed method.

Channel estimation in wireless OFDM systems using reservoir computing

According to recent reports and surveys over the last 2 years, field-programmable gate arrays (FPGAs) have increasingly become the prime targets for carrying out extremely sophisticated cyber-attacks. FPGAs incorporate runtime reconfiguration capabilities, which allow modular designs to be mapped. Low-end FPGAs are widely used in many networking applications where severe cost, power, and resource constraints persist. These constraints force a tradeoff for FPGA developers regarding FPGA security features such as encryption of FPGA bitstreams. As a result, critical security issues arise, such as hardware Trojan (HT) insertion. Attackers can attempt to gain control of the FPGA during run-time for Trojan insertion by bitstream reverse engineering. In this paper, we turn the tables and provide a proof of concept for an approach that utilizes bitstream reverse engineering for Trojan detection. Our approach is bottom-up: it starts with bitstream inspection, FPGA component identification from the layout, and follows up with identification of malicious configurations. Due to this bottom-up approach, any stealthy malicious circuit can be detected, which is difficult to achieve through conventional design analysis methods. We leverage open-source tools, publicly available datasets and vendor provided tools. The method is generic and can be applied to a wide range of FPGAs. An example of Trojan detection is shown for Xilinx Virtex5 VLX50T FPGA. Once a reference database is created, the Trojan detection is very fast and takes less than a minute on a general-purpose Intel Core i5 processor-based computer. The proposed Trojan detection approach is, to the best of our knowledge during publication, the only open source, software-based, low-cost alternative to time consuming design re-construction and analysis based approaches. It can be applied at the customer end without requiring any hardware alteration/IP updates from FPGA vendors.

Turning the Table: Using Bitstream Reverse Engineering to Detect FPGA Trojans

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