3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional microarchitecture between two die in a stack Results: It is shown that a 32MB 3D stacked DRAM cache can reduce the cycles per memory access of a twothreaded RMS benchmark on average by 13% and as much as 55% while increasing the peak temperature by a negligible 0.08?C. Off-die BW and power are also reduced by 66% on average. It is also shown that a 3D floorplan of a high performance microprocessor can simultaneously reduce power 15% and increase performance 15% with a small 14?C increase in peak temperature. Voltage scaling can reach neutral thermals with a simultaneous 34% power reduction and 8% performance improvement.

Die Stacking (3D) Microarchitecture

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The fabrication of digital Integrated Circuits (ICs) is increasingly outsourced. Given this trend, security is recognized as an important issue. The threat agent is an attacker at the IC foundry that has information about the circuit and inserts covert, malicious circuitry. The use of 3D IC technology has been suggested as a possible technique to counter this threat. However, to our knowledge, there is no prior work on how such technology can be used effectively. We propose a way to use 3D IC technology for security in this context. Specifically, we obfuscate the circuit by lifting wires to a trusted tier, which is fabricated separately. This is referred to as split manufacturing. For this setting, we provide a precise notion of security, that we call k-security, and a characterization of the underlying computational problems and their complexity. We further propose a concrete approach for identifying sets of wires to be lifted, and the corresponding security they provide. We conclude with a comprehensive empirical assessment with benchmark circuits that highlights the security versus cost trade-offs introduced by 3D IC based circuit obfuscation.

/pdf/securing-computer-hardware-using-3d-integrated-circuit-ic-5cwrt2tyfe.pdf

Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation

The field of spintronics has attracted tremendous attention recently owing to its ability to offer a solution for the present-day problem of increased power dissipation in electronic circuits while scaling down the technology. Spintronic-based structures utilize electron’s spin degree of freedom, which makes it unique with zero standby leakage, low power consumption, infinite endurance, a good read and write performance, nonvolatile nature, and easy 3D integration capability with the present-day electronic circuits based on CMOS technology. All these advantages have catapulted the aggressive research activities to employ spintronic devices in memory units and also revamped the concept of processing-in-memory architecture for the future. This review article explores the essential milestones in the evolutionary field of spintronics. It includes various physical phenomena such as the giant magnetoresistance effect, tunnel magnetoresistance effect, spin-transfer torque, spin Hall effect, voltage-controlled magnetic anisotropy effect, and current-induced domain wall/skyrmions motion. Further, various spintronic devices such as spin valves, magnetic tunnel junctions, domain wall-based race track memory, all spin logic devices, and recently buzzing skyrmions and hybrid magnetic/silicon-based devices are discussed. A detailed description of various switching mechanisms to write the information in these spintronic devices is also reviewed. An overview of hybrid magnetic /silicon-based devices that have the capability to be used for processing-in-memory (logic-in-memory) architecture in the immediate future is described in the end. In this article, we have attempted to introduce a brief history, current status, and future prospectus of the spintronics field for a novice.

/pdf/spintronic-devices-a-promising-alternative-to-cmos-devices-x2ekn7iv7a.pdf

Spintronic devices: a promising alternative to CMOS devices

As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the chip. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3-D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional two-dimensional integrated circuits (2-D ICs). In this paper, thermal vias are assigned to specific areas of a 3-D IC and used to adjust their effective-thermal conductivities. The method, which uses finite-element analysis (FEA) to calculate temperatures quickly during each iteration, makes iterative adjustments to these thermal conductivities in order to achieve a desired thermal objective and is general enough to handle a number of different thermal objectives such as achieving a desired maximum operating temperature. With this method, 49% fewer thermal vias are needed to obtain a 47% reduction in the maximum temperatures, and 57% fewer thermal vias are needed to obtain a 68% reduction in the maximum thermal gradients than would be needed using a uniform distribution of thermal vias to obtain these same thermal improvements. Similar results were seen for other thermal objectives, and the method efficiently achieves its thermal objective while minimizing the thermal-via utilization.

http://www.ee.umn.edu/users/sachin/jnl/tcad06bg.pdf

Placement of thermal vias in 3-D ICs using various thermal objectives

Advancements in IC manufacturing technologies allow for building very large devices with billions of transistors and with complex interactions between them encapsulated in a huge number of design rules. To ease designers' efforts in dealing with electrical and manufacturing problems, regular layout style seems to be a viable option. In this paper we analyze regular layouts in an IC manufacturability context and define their desired properties. We introduce the OPC-free IC design methodology and study properties of cells designed for this layout style that have various degrees of regularity.

OPC-free and minimally irregular IC design style

Defect density and size distributions (DDSDs) are important parameters for characterizing spot defects in a process. This article addresses random spot defects, which affect all processes and currently require a heavy silicon investment to characterize and a new approach is proposed for characterizing such defects. This approach presents a system that overcomes the obstacle of silicon area overhead by using available wafer sort test results to measure critical-area yield model parameters with no additional silicon area. The results of the experiment on chips fabricated in silicon confirm the results of the simulation experiment that DDSDs measurement characterizes a process in ordinary digital circuits using only slow, structural test results from the product

/pdf/extracting-defect-density-and-size-distributions-from-2pus2vdk2z.pdf

Extracting Defect Density and Size Distributions from Product ICs

Diagnosis algorithms for integrated circuits (ICs) are typically developed and evaluated using a limited number of logic-level models of defect behaviors. However, it is well-known that real IC defects exhibit behavior well outside these models. Consequently, the utility of IC diagnosis methodologies may be uncertain. A simulation-based benchmarking strategy is developed that uses circuit-level models to describe the complex nature of real defects. Specifically, we have proposed a simple yet powerful strategy using a small circuit and a set of bounded deformations (i.e., defects) for measuring the effectiveness of diagnosis techniques. Evaluation of several simple and commercial diagnosis algorithms indicates that this form of diagnosis benchmarking is viable.

Benchmarking diagnosis algorithms with a diverse set of IC deformations

Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used to estimate these distributions. In this paper, we propose a strategy to accurately estimate DDSDs for shorts in metal layers using production IC test results.

/pdf/extraction-of-defect-density-and-size-distributions-from-1pu5bofof8.pdf

Extraction of Defect Density and Size Distributions from Wafer Sort Test Results

This paper investigates a 3D die-stacking based VLSI integration strategy, so-called 2.5D integration, which can potentially overcome many problems stumbling the development of monolithic System-on-Chip (SoC). In this paper, we review available fabrication technologies and testing solutions for the new integration strategy. We also propose a design driven system implementation schema for this new integration strategy. A layout synthesis framework is under development by us to analyze typical "what if" questions and resolve major physical attributes for a 2.5D system according to the design specification and constraints.

2.5D system integration: a design driven system implementation schema

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