In all digital systems, data conversion is the main process that is done with the help of an Analog to digital converter. There are many types of ADC’s available for this conversion but among those Flash, ADCs are more advantageous because of their high speed. Flash ADC has a high speed due to the simultaneous conversion. The addition of the comparator delays and the logic delays (logic delays are negligible) gives the conversion speed of flash ADC. So, Flash ADC is one of the most commonly used ADC in high-speed applications. But even though it has high speed its area and power requirement are also more if we consider conventional Flash ADC. To enhance the performance of the Flash ADC the advanced architecture of ADC is proposed using the information of the half Flash ADC in which conversion happens in two steps. For 8-Bit half Flash ADC, the first higher 4-Bits are calculated. And then in the second step remaining 4 -Bits are calculated. Flash ADC also requires a large no of components so it is difficult to use it under any microcontroller. Hence in the proposed work, ADC is designed to reduce the complexity of conventional Flash ADC and to achieve less area and less power consumption. This model is designed based on half Flash ADC only difference is that here Bitwise conversion happens. It uses 2N − 1 operational amplifiers with the elimination of DAC and encoders which makes the circuit suitable for use inside the micro controller. The proposed work explains the design and implementation of 3-Bit Advanced Flash ADC architecture with Error correction. 

Advanced Architecture of Analog to Digital Converter Derived from Half Flash ADC

Digital calibration using adaptive signal processing corrects offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10b 120MSample/s pipelined ADC. With background calibration, peak SNDR is 56.8dB and power dissipation is 234mW from 3.3V. Active area is 12.5mm/sup 2/ in 0.35/spl mu/m CMOS.

A 10bit 120MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration

A conventional N-bit flash analog to digital converter has been required the 2N number of resistors and 2N-1 number of preamplifiers as well as comparators. In this proposed work, a number of comparators could be reduced by introducing the multiplexer (MUX). This proposed work has only required the (2^(N-2) + 1) number of comparators. For 6-bit resolution, MUX based flash ADC requires a reduced number of comparators by 73%, respectively, compared with the traditional flash ADC. This proposed 6-bit ADC consists of a reference ladder circuit, a (2x1) multiplexer, 8 (4x1) multiplexer, 17 comparators and thermometer to binary encoder. The proposed 6-bit 200 MSPS ADC is designed and simulated in cadence tools with 1 V supply voltage using 90nm CMOS technology. The proposed work results into effective number of bits (ENOB) of 5.69 bit and figure of merit (FOM) of 0.019 pJ/conversion-step for 200 MS/s.

MUX Based Flash ADC for Reduction in Number of Comparators

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MUX Based Flash ADC for Reduction in Number of Comparators