A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10-15 is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm2 per TX/RX pair

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

Limitations in current backplane environments impede high-speed data transmission above 5 Gb/s. A system architecture to extend the transmission capacities of legacy backplanes is proposed. The incentives for using a four-level pulse amplitude modulation (4-PAM) scheme are also presented. The architecture is built from feed-forward equalizer and tunable filter elements for near-end crosstalk noise cancellation. Each of the circuits is implemented in a standard 0.18-/spl mu/m CMOS process. The building blocks of the architecture, which include an LC ladder, a modified Gilbert-cell multiplier with improved headroom, and a tunable active high-pass filter are described in detail. Results of the architecture are shown demonstrating 20-Gb/s 4-PAM signal transmission.

Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally spaced FIR equalizer is demonstrated using a low-power and area-efficient pulse extraction method as on-chip error detector. Measurement results show that the proposed adaptive equalizer achieves over 75% horizontal eye opening when the channel loss at the half-data-rate frequency varies from 4 dB to 21 dB at 2.5-Gb/s data rate. At 3.5-Gb/s data rate, the equalizer achieves 68% horizontal eye opening when the channel loss is about 9.3 dB at the half-data-rate frequency. The adaptive equalizer including the FIR filter and the error detector occupies 0.095 mm2 die area and dissipates 95 mW at 2.5-Gb/s data rate from 2.5-V voltage supply

A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25- $muhbox m$ CMOS

To ensure the signal integrity over a lossy channel, an analog equalizer and/or a decision-feedback equalizer (DFE) [2–6] are widely adopted in high-speed data transmission An adaptive analog equalizer or adaptive DFE is also attractive to compensate the frequency-dependent loss due to the different channel lengths and environment variations Conventionally, a multiple-tap DFE is adopted to compensate the inter-symbol interference (ISI), which is induced by postcursors due to the non-ideal channel impulse responses To avoid the power and area penalty due to many postcursors, a DFE with infinite impulse response (IIR) filter feedback [2] has been presented In [2], no adaptation scheme ensures that such IIR filter cancels the postcursors precisely, ie, its RC time constant and amplitude need to be manually adjusted In this work, a 6Gb/s receiver using a DFE with an adaptive continuous-time IIR filter and a clock/data recovery (CDR) circuit is presented In a high loss environment, a conventional digital qaudricor-relator frequency detector (QFD) may fail due to the significant data dependent jitter To integrate an adaptive DFE with a CDR circuit, a proposed frequency-sweeping frequency detector (FD) and a lock detector (LD) are presented in this work

A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization

A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A BER<10/sup -15/ is measured over legacy backplane channels.

with First Post-Cursor Tap Cancellation for Serial Backplane Communications

Feedforward Equalization for 6.25/12.5Gb/s Serial Backplane Communications

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Vikas Gupta

Author Tools

Chat about Author

Papers

with First Post-Cursor Tap Cancellation for Serial Backplane Communications

Feedforward Equalization for 6.25/12.5Gb/s Serial Backplane Communications