An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

Embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided. The example gas channel plate includes a heat exchange surface including a plurality of heat exchange structures separated from one another by intervening gaps. The example gas channel plate also includes a heat exchange fluid director plate support surface for supporting a heat exchange fluid director plate above the plurality of heat exchange structures so that at least a portion of the plurality of heat exchange structures are spaced from the heat exchange fluid director plate.

Process feed management for semiconductor substrate processing

A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes while reducing the concentration of the inert gas, such as Ar, to 0-13% of the total process gas flow. By reducing the inert gas concentration, sputtering or etching is reduced, resulting in reduced sidewall deposition from the sputtered material. Consequently, gaps with aspect ratios of 3.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.

High aspect ratio gapfill process by using HDP

Methods and structures relating to the formation of mixed SAMs for preventing undesirable growth or nucleation on exposed surfaces inside a reactor are described. A mixed SAM can be formed on surfaces for which nucleation is not desired by introducing a first SAM precursor having molecules of a first length and a second SAM precursor having molecules of a second length shorter than the first. Examples of exposed surfaces for which a mixed SAM can be provided over include reactor surfaces and select surfaces of integrated circuit structures, such as insulator and dielectric layers.

Reactive site deactivation against vapor deposition

A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Method for selective deposition of a thin self-assembled monolayer

A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Methods for selective integration of airgaps and devices made by such methods

In one embodiment, the present invention provides a method of forming a dynamic random access memory device which utilizes self-aligned contact pads 40 a and 40 b for the bit line and storage node contacts. A transfer gate 14 is formed at the fact of a semiconductor region 30. The semiconductor 30 includes a bit line contact region 44 and storage node contact region adjacent opposite edges of the transfer gate 14. Transfer gate 14 is surrounded with an insulating material 34/38. A conductive layer 40 is formed over the transfer gate 14, over the bit line contact region 44 and over the storage node contact region. This conductive layer 40 is then etched so that a first portion 40 a of the conductive layer 40 provides an electrical contact to the bit line contact region 44 and a second portion 40 b of the conductive layer 40 provides an electrical contact to the storage node contact region. The bit line 18 and storage node electrode 22 can then be formed in electrical contact with the first and second portions of the conductive layer 40 a and 40 b , respectively.

Method of forming a memory cell with self-aligned contacts

A sputter-etch process is used to etch vias having substantially vertical sidewalls, such that a sloped sidewall is formed. Using a silicon dioxide layer in which to form the vias, slopes of approximately 45° may be obtained. A second insulator layer may be provided to protect the leads and other portions of the device during the sputter-etch to prevent damage.

Method of forming a via having sloped sidewalls

A method for deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is disclosed comprising the steps of depositing a first self-assembled monolayer (13) to said surface, depositing a second self-assembled monolayer (8) to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

A method for deposition of a thin selfassembled mono-layer (SAM)

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