Vaidyanathan Kripesh
Agency for Science, Technology and Research
7 Papers
314 Citations
Vaidyanathan Kripesh is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Layer (electronics) & Copper interconnect. The author has an hindex of 4, co-authored 7 publications. Previous affiliations of Vaidyanathan Kripesh include Singapore Science Park.
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Papers
Patent
Wafer-level package for micro-electro-mechanical systems
Ranganathan Nagarajan,C.S. Premachandran,Yu Chen,Vaidyanathan Kripesh +3 more
- 27 Jan 2003
TL;DR: In this article, a method for forming wafers having through-wafer vias for wafer-level packaging of devices is proposed, which consists of depositing a metal layer on one of a first wafer and a second wafer; bonding the first waf and the second waf using the metal layer deposited on one each wafer, forming a throughwafer via in one of the first Wafer and the other Wafer; filling the through-Wafer via with a conductive material; and forming a cavity in the one of WF and the
192
Patent
RF and MMIC stackable micro-modules
Vaidyanathan Kripesh,Mihai Rotaru,Ganesh Vetrivel Periasamy,Seung Uk Yoon,Ranganathan Nagarajan +4 more
- 23 May 2007
TL;DR: In this article, a new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved, which comprises, first, providing a substrate.
80
Patent
Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices
Vaidyanathan Kripesh,Seung Wook Yoon,Ganesh Vetrivel Periasamy +2 more
- 12 Oct 2004
TL;DR: In this paper, a process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor device are protected during device processing sequences and dicing procedures, has been developed.
34
Patent
Semiconductor structure and a method of manufacturing a semiconductor structure
Navas Khan Oratti Kalandar,Vaidyanathan Kripesh,Xiaowu Zhang,Chee Houe Khong +3 more
- 28 May 2008
TL;DR: In this article, a semiconductor structure consisting of a first support structure, a plurality of chips formed on the first support and a reinforcing structure was provided, the reinforcing structure including an outer surrounding element which surrounded the plurality and extended from a surface of the first base to a height higher than each of the chips.
4
Patent
Wafer level packages and methods of fabrication
Vaidyanathan Kripesh,Wai Kwan Wong,Mihai Rotaru,Tai Chong Chai,M.K. Iyer +4 more
- 10 Sep 2004
TL;DR: In this paper, a wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed, which comprises at least one first, second and third separation layer having at least first and second conductive layer formed in-between the separation layers.
4