This paper presents a low power switchable current mode driver/receiver I/O pair for high speed serial transmission of asynchronous address event representation (AER) information. The sparse nature of AER packets (also called events) allows driver/receiver bias currents to be switched off to save power. The on/off times must be lower than the bit time to minimize the latency introduced by the switching mechanism. Using this technique, the link power consumption can be scaled down with the event rate without compromising the maximum system throughput. The proposed technique has been implemented on a typical push/pull low voltage differential signaling (LVDS) circuit, but it can easily be extended to other widely used current mode standards, such as current mode logic (CML) or low-voltage positive emitter-coupled logic (LVPECL). A proof of concept prototype has been fabricated in 0.35 μm CMOS incorporating the proposed driver/receiver pair along with a previously reported switchable serializer/deserializer scheme. At a 500 Mbps bit rate, the maximum event rate is 11 Mevent/s for 32-bit events. In this situation, current consumption is 7.5 mA and 9.6 mA for the driver and receiver, respectively, while differential voltage amplitude is ±300 mV. However, if event rate is lower than 20-30 Kevent/s, current consumption has a floor of 270 μA for the driver and 570 μA for the receiver. The measured ON/OFF switching times are in the order of 1 ns. The serial link could be operated at up to 710 Mbps bit rate, resulting in a maximum 32-bit event rate of 15 Mevent/s . This is the same peak event rate as that obtained with the same SerDes circuits and a non-switched driver/receiver pair.

A ${0.35}~\mu{\rm m}$ Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links

This article presents a reconfigurable silicon- photonics transmitter (TX) for short-reach optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver with a 180-nm SOI-CMOS silicon-photonic Mach-Zehnder Modulator (MZM). The driver integrated with in- segment fractional-UI spaced feed-forward equalizer (FFE) is proposed to support the non-return-zero (NRZ) signaling, electrical- and optical-domain 4-level pulse-amplitude modulation (PAM-4) signaling. The driver employs a reconfigurable distributed topology to achieve high swing, wide bandwidth and flexible operation. The MZM is driven differentially in a push-pull configuration for high modulation efficiency. Measurement results show that the proposed TX operates up to 50-Gb/s NRZ data rate with 4-Vppd swing and 1.92-ps RMS jitter. In the optical PAM-4 mode, it reaches 56-Gb/s data rate and achieves &#x003E;5-dB extinction ratio (ER) at the cost of 10.9-pJ/bit power efficiency. 

A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS

A low power source-synchronous source-series-terminated (SST) transmitter (Tx) in 65 nm CMOS technology is presented. The Tx, comprised of nine data/control channels, a forwarded-clock channel and one PLL, merely dissipates 26.2 mW/channel while exhibiting a 750 mV differential eye height at 6.4 Gbps. The SST drivers can save ¾ output stage power of CML ones, and moreover, the proposed novel topology can independently control impedance self-calibration and equalization. To implement half-rate architecture, the PVT-tolerant PLL provides a pair of quadrature clocks with 2.5 ps rms cycle to cycle jitters running at 3.2 GHz.

/pdf/a-novel-sst-transmitter-with-mutually-decoupled-impedance-1en2lp4qu0.pdf

A novel SST transmitter with mutually decoupled impedance self-calibration and equalization

A low-power voltage-mode-logic (VML) transmitter fabricated in TSMC 28 nm CMOS technology is presented. The VML driver outputs a high-swing signal and consumes less power than a current-mode-logic (CML) driver. To further reduce power, the driver is divided into two voltage domains by level shifters. Moreover, the proposed driver topology can achieve mutually decoupled impedance self-calibration and equalization control. The measurement result shows that the transmitter merely dissipates 23 mW/channel while exhibiting an 880 mV differential eye height at 4.488 Gb/s.

A low-power high-swing voltage-mode transmitter

This paper presents a new topology of a PMOS based LVDS voltage-mode output driver. This topology is designed to meet the requirements of low power consumption and high data rates applications. The driver, which consists of a pre-driver stage and an output stage, uses a positive feedback technique at the output stage to achieve line impedance matching and power saving. The pre-driver stage is used to set the driver's swing and common mode output voltage. The pre-driver and the output stage consume only 9mW of power at 3 Gbps speed while operating from a 1.8V voltage supply. The system is designed and simulated using CMOS 180nm technology and is fully compliant with LVDS output swing and common mode voltage specifications.

A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver

This paper describes a new topology and implementation of a 10-Gbits/s low-voltage differential-signaling (LVDS) voltage-mode output driver designed for high-speed data-transfer applications. Using a positive-feedback technique, the driver achieves ultralow-power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized, and good signal integrity is achieved. The driver, which consists of a predriver and an output stage, consumes a total of 15.63-mW at-speed power. In measurements, the driver, which was a part of an equalizer chip, achieved a peak-to-peak jitter of 11 ps at 10 Gbits/s and a return-loss performance of less than -15 dB. It provides a single-ended output swing of 400 mV and a common-mode voltage of 1.25 V, which are compliant with LVDS standards. The chip is fabricated in a standard 2.5-V/1.2-V SiGe BiCMOS technology with 100-GHz peak ft and is packaged in a commercial LLP package.

An Ultralow-Power 10-Gbits/s LVDS Output Driver

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An Ultralow-Power 10-Gbits/s LVDS Output Driver