Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive the requirements that optical components must meet.

https://www.csl.cornell.edu/%7Ealbonesi/research/papers/groupIV.pdf

On-chip optical interconnect roadmap: challenges and critical directions

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

Interconnect has become a primary bottleneck in integrated circuit design As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies Electrical and optical interconnects are compared for various design criteria based on these predictions The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node

Predictions of CMOS compatible on-chip optical interconnect

This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 erms- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e-·nJ.

A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture

Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanism, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC domain. This paper presents a survey of techniques for energy efficient on-chip communication. Techniques operating at different levels of the communication design hierarchy are described, including circuit-level techniques, such as low voltage signaling, architecture-level techniques, such as communication architecture selection and bus isolation, system-level techniques, such as communication based power management and dynamic voltage scaling for interconnects, and network-level techniques, such as error resilient encoding for packetized on-chip communication. Emerging technologies, such as Code Division Multiple Access (CDMA) based buses, and wireless interconnects are also surveyed.

A survey of techniques for energy efficient on-chip communication

In large chips, the propagation delay of the data and clock signals is limited due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current. Design equations for determining the optimum number of repeaters to be inserted along a resistive interconnect line for reduced delay are presented. Power dissipation in repeater chains is also analyzed. The analytical model used in these design equations is based on the /spl alpha/-power law I-V equations for modeling short-channel devices and exhibits a maximum error of 16% for typical RC loads as compared to SPICE.

http://ieeexplore.ieee.org/iel3/4816/13529/00621595.pdf

Repeater design to reduce delay and power in resistive interconnect

A delay and power model of a CMOS inverter driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha power law and exhibits good accuracy. The model can be used to design and analyze those inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay, transition time, and short circuit power dissipation for a CMOS inverter driving resistive-capacitive interconnect lines.

/pdf/delay-and-power-expressions-for-a-cmos-inverter-driving-a-t4snvwkb77.pdf

Delay and power expressions for a CMOS inverter driving a resistive-capacitive load

The semiconductor industry standard computer-aided-design (CAD) tool Cadence has been calibrated for a 3 /spl mu/m Niobium technology in order to design and build superconductive single flux quantum (SFQ) circuits. The top-down design methodology includes Verilog functional simulation, schematic capture, graphic layout, functional verification, design rule checking, electrical rule checking, and layout-vs.-schematic verification. This design framework has been used successfully at the University of Rochester in designing more than 15 elementary SFQ cells and three large scale digital and mixed-signal SFQ circuits, demonstrating significant improvement in both design efficiency and accuracy.

A Cadence-based design environment for single flux quantum circuits

One method of overcoming wire delay due to long resistive interconnect is to insert repeaters in the line. Analytical expressions describing a CMOS inverter driving an RC load have been integrated into a global optimization algorithm for inserting repeaters into RC trees. The timing model predicts results generally within 10% of SPICE. The global optimization method exhibits total delay improvements of up to 86% over typical cascaded buffer insertion methods. The repeater timing model, global insertion methodology and algorithm, and software implementation are summarized in this paper.

Optimizing RC tree delay in high speed ASICs through repeater insertion

A delay and power model of a CMOS inverting repeater driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time and exhibit less than 27% discrepancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a resistive-capacitive interconnect line which are accurate to within 15% of SPICE for most practical loads.

Timing and power models for CMOS repeaters driving resistive interconnect

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