Book review: Applied cryptography: Protocols, algorithms, and source code in C

The IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. All members of the IEEE are eligible for membership in all three societies upon payment of membership fee. For membership and subscription information and pricing, please visit www.ieee.org/membership-catalog.

IEEE transactions on very large scale integration (VLSI) systems

A method to detect hardware Trojan in gate-level netlist is proposed using deep learning technique. The paper shows that it is easy to identify genuine nodes and Trojan-infected nodes based on controllability and transition probability values of a given Trojan-infected circuit. The controllability and transition probability characteristics of Trojan-infected nodes show large inter-cluster distance from the genuine nodes so that it is easy to cluster the nodes as Trojan-infected nodes and genuine nodes. From a given circuit, controllability and transition probability values are extracted as Trojan features using deep learning algorithm and clustering the data using k-means clustering. The technique is validated on ISCAS’85 benchmark circuits, and it does not require any golden model as reference. The proposed method can detect all Trojan-infected nodes in less than 6 s with zero false positive and zero false negative detection accuracy.

Hardware Trojan Detection Using Deep Learning Technique

To remain dormant in the validation and manufacturing test, Trojans tend to have at least one trigger signal at the gate-level netlist with a very low transition probability. Our paper exploits this stealthy nature of trigger signals to detect Trojans using static and dynamic transition probabilities. The proposed trigger identification is a reference-free scheme, and no prior knowledge of a Trojan-free design is required. First, we reveal the relation between combinational 0/1-controllability and 0/1-probability and propose a static transition probability analysis based on our proposed difference-amplified controllability, which can be easily obtained by the Sandia Controllability/Observability Analysis Program. The k-means clustering method is adopted for potential trigger classification to extend the scalability and adaptability to different circuit sizes. Second, we propose to utilize the transition probability of a dynamic simulation for correction of the results. Experiments show that the proposed detection scheme can obtain a 0% false negative rate and a maximum 11.7% false positive rate on Trust-HUB benchmarks.

Trigger Identification Using Difference-Amplified Controllability and Dynamic Transition Probability for Hardware Trojan Detection

A new CMOS Analog Multiplier in Current Domain using very negligible amount of static power is presented. This circuit uses the concept of harmonics along with the square law of current in a saturated MOS and is simulated using 90nm Technology Node of UMC. The supply voltage Vdd is kept at +1V. The circuit, when drawn using the Cadence Virtuoso Schematic Editor and simulated using the Spectre Simulator, gave a -3dB bandwidth of 2.07GHz with a load capacitance of 10fF.

Progress in VLSI Design and Test

As a result of the emergence of new fabrication technologies and design complexities, standard stuck-at scan tests are no longer sufficient. The number of tests and corresponding data volume increase with each new fabrication process technology. The demand goes to well beyond 100X tester cycle reduction considering new fault models. The test data compression has been an emerging need of VLSI field and the hot topic of research for last decade. Still there is a great need and scope for further reduction in test data volume. This reduction must be lossless for input side test data. This paper summarizes the different methods based on coding theory applied for lossless compression of the input side test data. It covers starting with simple code based methods to combine/hybrid methods. The basic goal here is to prepare survey on current methodologies applied for test data compression and prepare a platform for further development in this avenue.

Survey of Test Data Compression Technique Emphasizing Code Based Schemes

QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.

Defect characterization and testing of QCA devices and circuits: A survey

A compression-decompression scheme, Modified Selective Huffman (MS-Huffman) scheme based on Huffman code is proposed in this paper. This scheme aims at optimization of the parameters that influence the test cost reduction: the compression ratio, on-chip decoder area overhead and overall test application time. Theoretically, it is proved that the proposed scheme gives the better test data compression compared to very recently proposed encoding schemes for any test set. It is clearly demonstrated with a large number of experimental results that the proposed scheme improves the test data compression, reduces overall test application time and on-chip area overhead compared to other Huffman code based schemes.

Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead

This paper presents a method to compress partially specified test data for a given SoC in Automatic Test Equipment (ATE). A method “Hamming Distance Based 2-Dimensional Reordering with Power Efficient Don't Care Bit Filling” is presented for compression of test data in which two dimensional i.e. row and columnwise test vector reordering and power optimized don't care bit filling method is applied. The advantage of the approach is a good compression with very low test power achieved without adding area overhead. The advantages are shown by experimental results with ISCAS benchmark circuits.

Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method

Traditionally, Hardware is considered as root of trust. Software generally builds on top of the hardware. By emerging Hardware Trojan attacks, this trust seems to be violated. Hardware Trojan is any addition or modification to a circuit or a system with malicious intention. Trojan can cause change or control over functionality in circuit or it may leak sensitive information from inside the chip and hence reduce circuit reliability. In this paper, we analyze threats caused by hardware Trojan attacks and type of hardware Trojans. We have discussed state-of-art hardware Trojan protection schemes. The limitations and challenges related to those trojan detection schemes are described. We also propose simple but effective probabilistic method to detect and find the location of hardware trojan in combinational circuits. The experimental results for a series of ISCAS85 benchmark circuits show that better trojan detection rate or coverage can be achieved with proposed technique.

Transition probabilistic approach for detection and diagnosis of Hardware Trojan in combinational circuits

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