This chapter introduces Chess, a retargetable code generation environment for fixedpoint DSP processors. Chess addresses a range of commercial as well as applicationspecific processors, which are increasingly being used for embedded applications in telecommunications, speech and audio processing. Chess is based on a mixed behavioural/structural processor representation model, which can account for many architectural peculiarities that are typical for fixed-point DSP processors. In addition, the code generator is employing a number of efficient optimisation techniques. These features result in highly optimal machine code.

Chess : Retargetable Code Generation for Embedded DSP Processors

This paper presents new techniques in two different areas. Firstly, it proposes a solution to the problem of testing embedded processors. Towards this end, it discusses the automatic generation of executable test programs from a specification of test patterns for processor components. Secondly, the paper shows how constraint logic programming (CLP) improves the software production process for design automation tools. The advantages of CLP languages include: built-in symbolic variables and the built-in support for constraints over finite domains such as integers and Booleans.

/pdf/retargetable-self-test-program-generation-using-constraint-9izy9zwss5.pdf

Retargetable Self-Test Program Generation Using Constraint Logic Programming

Software synthesis is a new approach which focuses on the support of embedded systems without the use of operating-systems. Compared to traditional design practices, a better utilization of the available time and hardware resources can be achieved with software synthesis, because the static information provided by the system specification is fully exploited and a application specific solution is automatically generated.In this paper on-going research on a software synthesis approach for real-time information processing systems is presented which starts from a concurrent process system specification and tries to automate the mapping of this description to a single processor. An internal representation model which is well suited for the support of concurrency and liming constraints is proposed, together with flexible execution models for multi-tasking with real-time constraints. The method is illustrated on a personal terminal receiver demodulator for mobile satellite communication.

Software Synthesis for real-time information processing systems.

Software synthesis for real-time information processing systems

This paper presents an automatic method for generating valid SDRAM command schedules which obey the timing restrictions of DDR2 memory from a set of memory references. These generated schedules can be implemented using a static memory controller. A complete knowledge of the sequence of memory references in an application enables the scheduling algorithm to reorder memory commands effectively to reduce latency and improve throughput. While statically scheduled command schedules might be considered too inflexible to be useful in mask-defined devices, they are well suited to implementation within an FPGA where new applications can be targeted by recompilation and reconfiguration. Static SDRAM schedules generated using our approach show a median 4x reduction in the number of memory stall cycles incurred across a selection of benchmarks when compared to schedules produced dynamically by the Altera High Performance Memory Controller.

http://cas.ee.ic.ac.uk/people/gac1/pubs/SamFPT09.pdf

Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search

This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with efficient constraint propagation techniques is an adequate programming environment for complex real world problems like high level synthesis, simulation, code generation, and memory synthesis. Different types of constraints — Boolean, integer, symbolic, structural, and type binding ones — are used to express relations between the components of a digital circuit and efficient propagation is achieved by the coroutining mechanism. To deal with the increasing complexity of digital circuits we use HDL's (hardware description languages) to represent structure and behaviour of circuits.

Application of Constraint Logic Programming for VLSI CAD Tools

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Application of Constraint Logic Programming for VLSI CAD Tools