A method and system for placing an order to purchase an item via the Internet. The order is placed by a purchaser at a client system and received by a server system. The server system receives purchaser information including identification of the purchaser, payment information, and shipment information from the client system. The server system then assigns a client identifier to the client system and associates the assigned client identifier with the received purchaser information. The server system sends to the client system the assigned client identifier and an HTML document identifying the item and including an order button. The client system receives and stores the assigned client identifier and receives and displays the HTML document. In response to the selection of the order button, the client system sends to the server system a request to purchase the identified item. The server system receives the request and combines the purchaser information associated with the client identifier of the client system to generate an order to purchase the item in accordance with the billing and shipment information whereby the purchaser effects the ordering of the product by selection of the order button.

Method and system for placing a purchase order via a communications network

In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Phase Change Memory

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The present invention is directed to secreted and transmembrane polypeptides and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

Secreted and Transmembrane Polypeptides and Nucleic Acids Encoding the Same

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

A gettering process for semiconductor manufacturing is disclosed. The gettering process is performed after device formation and after a protective layer such as (BPSG) or (PSG) has been applied to the front side of a semiconductor wafer. The gettering process includes thinning and roughening a backside of the wafer using chemical mechanical planarization (CMP). During the (CMP) dislocations are formed which function as a trap of mobile contaminants. Additionally a gettering agent such as phosphorus is deposited and diffused into the backside of the wafer. The wafer can then be annealed for driving in the gettering agent and segregating mobile contaminants in the wafer at gettering centers formed at the dislocations and at gettering agent sites within the wafer crystal structure. The annealing step may also function to reflow and planarize the (BPSG) or (PSG) protective layer.

Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion

An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturability of CMOS devices by dramatically reducing the number of photomasking steps required to fabricate transistors. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology. Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.

Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants

A process and structure for improving the conductive capacity of a polycrystalline silicon (poly) structure, such as a bit line. The inventive process allows for the formation of a refractory metal silicide layer on the top and sidewalls of a poly structure, thereby increasing the conductive capacity. To form the titanium silicide layer over the poly feature, the refractory metal is sputtered on the poly, which reacts to form the refractory metal silicide. A second embodiment is described whereby an isotropic etch of the poly feature slopes the sidewalls; then, the refractory metal is sputtered onto the polycrystalline silicon. This allows for the formation of a thicker layer of refractory metal silicide on the sidewalls, thereby further increasing the conductive capacitance of the poly structure. Suggested refractory metals include titanium, cobalt, tungsten, and tantalum.

Sidewall silicidation for improved reliability and conductivity

The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing a buried contact implant window to expose a portion of at least one spaced apart area and an adjacent field silicon dioxide end portion; implanting an N-type dopant through the buried implant contact window, the implant forming a first N-type diffusion region in the exposed spaced apart area and changing the etch rate of the exposed field silicon dioxide end portion; stripping the masking layer; growing a sacrificial silicon dioxide layer, over the field silicon dioxide regions and the spaced apart areas of the supporting silicon substrate, thereby annealing the exposed field silicon dioxide end portion and returning the etch rate of the exposed field silicon dioxide end portion to substantially the same etch rate as prior to the implantation step; stripping the sacrificial silicon dioxide layer; growing a gate silicon dioxide layer over the spaced apart areas; depositing a first polysilicon layer over the gate silicon dioxide layer; patterning a buried contact window in the first polysilicon layer, thereby exposing the first N-type diffusion region and re-exposing the field silicon dioxide end portion; depositing a second polysilicon layer superjacent the first polysilicon layer and patterning whereby the first polysilicon layer forms a gate over the gate and the second polysilicon layer makes direct contact to the first N-type diffusion region; wherein the dopants from the patterned doped polysilicon forms a second N-type diffusion region within the first N-type diffusion region.

Method of forming a low resistive current path between a buried contact and a diffusion region

A semiconductor memory device such as a dymanic random access memory (DRAM) is formed by first forming a burried contact in a silicon wafer and patterning a series of transistors. After the transistors are patterned, oxide layers are applied and the transistors are etched. Cell bottom plates are then formed and electrical connections between the transistors and a periphery are established. The establishment of the transistors are to forming the cell bottom plates and its more efficient manufacture of the DRAM devices and increases manufacturing yield.

Sequence of etching polysilicon in semiconductor memory devices

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