Tun Zainal Azni Zulkifli
Universiti Teknologi Petronas
49 Papers
148 Citations
Tun Zainal Azni Zulkifli is an academic researcher from Universiti Teknologi Petronas. The author has contributed to research in topics: CMOS & Low-noise amplifier. The author has an hindex of 9, co-authored 49 publications. Previous affiliations of Tun Zainal Azni Zulkifli include Universiti Sains Malaysia Engineering Campus & Petronas.
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Papers
Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications
TL;DR: Recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed.
Effect of Unit Cell Type and Pore Size on Porosity and Mechanical Behavior of Additively Manufactured Ti6Al4V Scaffolds.
Haizum Aimi Zaharin,Ahmad Majdi Abdul Rani,Farooq I. Azam,Turnad Lenggo Ginta,Nabihah Sallih,Azlan Ahmad,Nurul Azhani Yunus,Tun Zainal Azni Zulkifli +7 more
TL;DR: Investigation of the influence of cube and gyroid unit cell types, with pore size ranging from 300 to 600 µm, on porosity and mechanical behavior of titanium alloy (Ti6Al4V) scaffolds shows promising results for application in orthopedic implants.
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Low-Voltage Low-Power Integrable CMOS Circuit Implementation of Integer- and Fractional–Order FitzHugh–Nagumo Neuron Model
Farooq Ahmad Khanday,Nasir Ali Kant,Mohammad Rafiq Dar,Tun Zainal Azni Zulkifli,Costas Psychalinos +4 more
TL;DR: The low-voltage low-power sinh-domain (SD) implementations of integer- and fractional-order FitzHugh–Nagumo (FHN) neuron model have been introduced and the field-programmable analog array (FPAA) implementation of the model has been presented, and the proper functioning of themodel has been verified.
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Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits
TL;DR: This work aims to demonstrate the viability of RRAM in the design of ternary logic systems and shows a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency.
A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier
TL;DR: A concurrent dual-band low-noise amplifier targeted for W-LAN IEEE 802.11 a/b/g standards is designed using 0.13-CMOS process to attain the power-constrained simultaneous noise and input matching at 2.4 and 5.2 GHz.
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