Digital processing of speech signals

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

This article provides a review of current development and challenges in brain-inspired computing with memristors. We review the mechanisms of various memristive devices that can mimic synaptic and neuronal functionalities and survey the progress of memristive spiking and artificial neural networks. Different architectures are compared, including spiking neural networks, fully connected artificial neural networks, convolutional neural networks, and Hopfield recurrent neural networks. Challenges and strategies for nanoelectronic brain-inspired computing systems, including device variations, training, and testing algorithms, are also discussed.

Brain-inspired computing with memristors: Challenges in devices, circuits, and systems

The volume, veracity, variability, and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks, and open problems in the field of neuromemristive circuits for edge computing.

pdf/neuromemristive-circuits-for-edge-computing-a-review-1vvzn48two.pdf

Neuromemristive Circuits for Edge Computing: A Review

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

Hierarchical temporal memory (HTM) is a machine learning algorithm inspired by the information processing mechanisms of the human neocortex and consists of a spatial pooler (SP) and temporal memory (TM). In this paper, we develop circuits and systems to achieve the optimized design of an HTM SP, an HTM TM, and a memristive analog pattern matcher for pattern recognition applications. The HTM SP realizes an optimized hardware design through the introduction of mean overlap calculations and by replacing the threshold determination in the inhibition stage with a weighted summation operator over the neighborhood of the pixel under consideration. HTM TM is based on discrete analog memristive memory arrays and a weight update procedure. The operation of the proposed system is demonstrated for a face recognition problem, using the standard AR, ORL, and Yale databases, and for speech recognition, using the TIMIT database, with achieved accuracies of 87.21% and approximately 90%, respectively, given an SNR of 10 dB. Visual data processing using binary HTM SP features requires less storage and processing memory than required by the traditional processing methods, with the area and power requirements for its implementation being 0.096 mm2 and 1756 mW, respectively. The design of the TM circuit for a single pixel requires 23.85 ${\mu}\text{m}^{2}$ of area and 442.26 ${\mu}\text{W}$ of power.

Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition

Hierarchical temporal memory (HTM) is a cognitive learning algorithm intended to mimic the working principles of neocortex, part of the human brain said to be responsible for data classification, learning, and making predictions. Based on the combination of various concepts of neuroscience, it has already been shown that the software realization of HTM is effective on different recognition, detection, and prediction making tasks. However, its distinctive features, expressed in terms of hierarchy, modularity, and sparsity, suggest that hardware realization of HTM can be attractive in terms of providing faster processing speed as well as small memory requirements, on-chip area, and total power consumption. Despite there are few works done on hardware realization for HTM, there are promising results which illustrate effectiveness of incorporating an emerging memristor device technology to solve this open-research problem. Hence, this chapter reviews hardware designs for HTM with specific focus on memristive HTM circuits.

Introduction to Memristive HTM Circuits

Hierarchical Temporal Memory (HTM) is a neuromorphic algorithm that emulates the working principles of neocortex useful for solving image classification problems Image pixels are transformed to binary HTM feature vectors following a set of weighted synaptic operations that combines the principles of sparsity, hierarchy, and modularity The sparsity of input pixel selection and feature encoding is introduced by setting initial weights as random following a uniform distribution In contrast to this approach, we propose that sparsity can be achieved by a deterministic approach of setting the input weights based on local mean intensity of pixels as a window operation The initial binary weights are selected and are then multiplied by the original image pixels to either suppress inputs with low potential or preserve input pixels with high potential Feature selection is then performed by selecting high potential pixels, which are preserved and are greater than the mean of neighbouring pixels, and suppressing the rest The proposed design was verified on a face image recognition problem Results show that proposed approach not only allow to preserve feature sparsity, but also to increase recognition accuracy for image classification with HTM

Design and implication of a rule based weight sparsity module in HTM spatial pooler

Implementation of neuromorphic systems using memristive crossbar array (MCA) has emerged as a promising solution to enable low-power acceleration of neural networks. However, the recent trend to design deep neural networks (DNNs) for achieving human-like cognitive abilities poses significant challenges toward the scalable design of neuromorphic systems (due to the increase in computation/storage demands). Network pruning is a powerful technique to remove redundant connections for designing optimally connected (maximally sparse) DNNs. However, such pruning techniques induce irregular connections that are incoherent to the crossbar structure. Eventually, they produce DNNs with highly inefficient hardware realizations (in terms of area and energy). In this article, we propose TraNNsformer—an integrated training framework that transforms DNNs to enable their efficient realization on MCA-based systems. TraNNsformer first prunes the connectivity matrix while forming clusters with the remaining connections. Subsequently, it retrains the network to fine-tune the connections and reinforce the clusters. This is done iteratively to transform the original connectivity into an optimally pruned and maximally clustered mapping. We evaluated the proposed framework by transforming networks of different complexity based on multilayer perceptron (MLP) and convolutional neural network (CNN) topologies on a wide range of datasets (MNIST, SVHN, CIFAR10, and ImageNet) and executing them on MCA-based systems to analyze the area and energy benefits. Without accuracy loss, TraNNsformer reduces the area (energy) consumption by 28%–55% (49%–67%)of MLP networks and by 28%–48% (3%–39%) of CNN networks with respect to the original network implementations. Compared to network pruning, TraNNsformer achieves 28%–49% (15%–29%) area (energy) savings for MLP networks and 20%–44% (1%–11%) area (energy) saving for CNN networks. Furthermore, TraNNsformer is a technology-aware framework that allows mapping a given DNN to any MCA size permissible by the memristive technology for reliable operations.

TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks

Amplifiers are essential building blocks of a majority of the mixed signal circuits that are used in the development of cognitive computing architectures. Their implementation and use is challenged by the second order effects that dominate the MOSFET operations with reduction in the technology size and scale. The ability to program the amplifiers once fabricated becomes an even more challenging problem as it warrants the use of multiple circuit components that lowers circuit performance and in turn outweighs the advantages of generalisation abilities. In this paper, a reconfigurable set of amplifier circuits are proposed based on quantised conductance devices in combination with MOSFET devices. The presented circuits form the basic configurations for the memristor based amplifiers, and show promising performance results in terms of power dissipation, on-chip area and THD values.

On Design of Memristive Amplifier Circuits

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