Tim Oliver
Nanyang Technological University
5 Papers
65 Citations
Tim Oliver is an academic researcher from Nanyang Technological University. The author has contributed to research in topics: Reconfigurable computing & Sequence database. The author has an hindex of 5, co-authored 5 publications.
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Papers
Hyper customized processors for bio-sequence database scanning on FPGAs
Tim Oliver,Bertil Schmidt,Douglas L. Maskell +2 more
- 20 Feb 2005
TL;DR: This paper presents a new approach to bio-sequence database scanning using re-configurable FPGA-based hardware platforms to gain high performance at low cost and shows how hyper-customization at run-time can be used to further improve the performance.
MPI-HMMER-Boost: Distributed FPGA Acceleration
John Paul Walters,Xiandong Meng,Vipin Chaudhary,Tim Oliver,Leow Yuan Yeow,Bertil Schmidt,Darran Nathan,J. I. Landman +7 more
- 01 Sep 2007
TL;DR: This work presents a cluster-enabled hardware/software-accelerated implementation of the HMMER search tool hmmsearch, and shows that combining the parallel efficiency of a cluster with one or more high-speed hardware accelerators (FPGAs) can significantly improve performance for even the most time consuming searches.
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Integrating FPGA acceleration into HMMer
Tim Oliver,Leow Yuan Yeow,Bertil Schmidt +2 more
- 01 Nov 2008
TL;DR: A new reconfigurable architecture is presented to accelerate the two HMMer database search procedures hmmsearch and hmmpfam and it is described how this leads to significant runtime savings on off-the-shelf field-programmable gate arrays (FPGAs).
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High-speed Multiple Sequence Alignment on a reconfigurable platform
TL;DR: A linear systolic array is constructed to perform pairwise sequence distance computations using dynamic programming and results in an implementation with significant runtime savings on a standard FPGA.
7
Using reconfigurable hardware to accelerate multiple sequence alignment with ClustalW
TL;DR: This work presents a new approach to compute multiple sequence alignments in far shorter time using reconfigurable hardware, which results in an implementation of ClustalW with significant runtime savings on a standard off-the-shelf FPGA.