The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.


Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly 
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence 
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products 
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes



Table of Contents


Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

Electronic Design Automation: Synthesis, Verification, and Test

Automatic circuit placement has received renewed interest recently given the rapid increase of circuit complexity, increase of interconnect delay, and potential sub-optimality of existing placement algorithms [13]. In this paper we present a generalized force-directed algorithm embedded in mPL2's [12] multilevel framework. Our new algorithm, named mPL5, produces the shortest wirelength among all published placers with very competitive runtime on the IBM circuits used in [29]. The new contributions and enhancements are: (1) We develop a new analytical placement algorithm using a density constrained minimization formulation which can be viewed as a generalization of the force-directed method in [16]; (2) We analyze and identify the advantages of our new algorithm over the force-directed method; (3) We successfully incorporate the generalized force-directed algorithm into a multilevel framework which significantly improves wirelength and speed. Compared to Capo9.0, our algorithm mPL5 produces 8% shorter wirelength and is 2X faster. Compared to Dragon3.01, mPL5 has 3% shorter wirelength and is 12X faster. Compared to Fengshui5.0, it has 5% shorter wirelength and is 2X faster. Compared to the ultra-fast placement algorithm: FastPlace, mPL5 produces 8% shorter wirelength but is 6X slower. A fast mode of mPL5 (mPL5-fast) can produce 1% shorter wirelength than Fast-Place1.0 and is only 2X slower. Moreover, mPL5-fast has demonstrated better scalability than FastPlace1.0.

Multilevel generalized force-directed method for circuit placement

Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently received much attention from both academia and industry. A novel and simple objective function for spreading cells over the placement area is described in the patent of Naylor et al. [26]. When combined with a wirelength objective function, this allows efficient simultaneous cell spreading and wirelength optimization using nonlinear optimization techniques. In this work, we implement an analytic placer (APlace) according to these ideas (which have other precedents in the open literature), and conduct in-depth analysis of characteristics and extensibility of the placer. Our contributions are as follows. (1) We perform analysis and empirical studies of relevant characteristics of the objective functions described in [26]. (2) We extend the objective functions with congestion information. (3) We implement a top-down hierarchical (multilevel) placer (APlace) based on the objective functions. The half-perimeter wirelength of APlace outperforms that of Cadence QPlace (SE5.4), UCLA Dragon (v3.01) and Capo (v8.7) respectively by 6.8%, 2.6% and 6.5% on average. When these placements are detail-routed using Cadence WRoute (SE5.4), the average improvement in final wirelength is 8.2%, 4.2% and 10.4% over QPlace, Dragon and Capo, respectively. (4) We extend the placer to perform I/O-core co-placement. I/Os can be evenly distributed without damaging the wirelength figure of merit. (5) We also extend the placer to handle constraints for mixed-signal designs (symmetry, alignment, etc.) and evaluate the impact of such constraints on runtime and wirelength.

Implementation and extensibility of an analytic placer

Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA technology over the past two decades. The purpose of this paper is to meet the demand for an up-to-date comprehensive survey/tutorial for FPGA design automation, with an emphasis on the recent developments within the past 5-10 years. The paper focuses on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow which includes: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. We hope that this paper can be used both as a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field.

/pdf/fpga-design-automation-a-survey-2zpbgytt2l.pdf

FPGA Design Automation: A Survey

Net weighting for timing-driven placement has been very popular in industry and academia. It has various advantages such as low complexity, high flexibility and ease of implementation. Existing net weighting algorithms, however, are often ad-hoc. There is generally no known good net weighting algorithms. In this paper, we present a novel net weighting algorithm based on the concept of path-counting, and apply it in a timing-driven FPGA placement application. Theoretically this is the first ever known accurate, all-path counting algorithm. Experimental data shows that compared with the weighting algorithm used in state-of-the-art FPGA placement package VPR (A. Marquardt et al, ACM Symp. on FPGAs, pp. 203-213, 2000), this new algorithm can achieve the longest path delay reduction of up to 38.8%, 15.6% on average with no runtime overhead and only a 4.1% increase in total wirelength.

A novel net weighting algorithm for timing-driven placement

Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.

/pdf/large-scale-circuit-placement-1zv9331sq7.pdf

Large-scale circuit placement

This paper presents several important enhancements to the recently published multilevel placement package mPL. The improvements include (i) unconstrained quadratic relaxation on small, noncontiguous subproblems at every level of the hierarchy; (ii) improved interpolation (declustering) based on techniques from algebraic multigrid (AMG), and (iii) iterated V-cycles with additional geometric information for aggregation in subsequent V-cycles. The enhanced version of mPL, named mPL2, improves the total wirelength result by about 12% compared to the original version. The attractive scalability properties of the mPL run time have been largely retained, and the overall run time remains very competitive. Compared to GORDIAN-L-DOMINO on uniform-cell-size IBM/ISPD98 benchmarks, a speed-up of well over 8/spl times/ on large circuits (/spl ges/100,000 cells or nets) is obtained along with an average improvement in total wirelength of about 2%. Compared to Dragon on the same benchmarks, a speed-up of about 5/spl times/ is obtained at the cost of about 4% increased wirelength. On the recently published PEKO synthetic benchmarks, mPL2 generates surprisingly high-quality placements-roughly 60% closer to the optimal than those produced by Capo 8.5 and Dragon-in run time about twice as long as Capo's and about 1/10th of Dragon's.

/pdf/an-enhanced-multilevel-algorithm-for-circuit-placement-49o5mfgv31.pdf

An Enhanced Multilevel Algorithm for Circuit Placement

This paper presents a model-assisted routing technique for improving lithography robustness of synthesized layouts.
Presupposing an accurate lithography model and a model-based layout weak spot identification procedure,
this method produces routed layout in-situ with acceptable turn around time. The approach starts with a
conventionally routed layout that, although conforming to design rules, may contain undesirable layout configurations
that the router should reconcile. Since weak spot identification is computation intensive, rule-based
filtering is first applied to the incoming layout to select regions for further model-based analysis. The router
then performs a non-discriminate correction to reduce the number of potential weak spots. This reduced set
subsequently undergoes model-based weak spot analysis, distinguishing the actual weak spots. The router finally
optimizes the layout to remove the identified weak spots.
This technique has been implemented in an industry detail router, and tested with 65-nm technology. Experimental
results show that this method can effectively remove actual weak spots with reasonable runtime.

Model-assisted routing for improved lithography robustness

Following logic synthesis and circuit design, an integrated circuit is represented as a collection of interconnected rectangular modules of fixed dimensions Timing constraints on signal propagation paths along sequences of connections are also specified The task of circuit placement is to arrange the modules inside a prescribed rectangular region such that no two modules overlap, timing constraints are satisfied, and the estimated total wirelength needed to implement the connections is minimized Thus, an algorithm for placement derives a suitable spatial characterization of a given circuit from a logical-temporal one

Multilevel Circuit Placement

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