A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Nonvolatile semiconductor memory device and method for manufacturing same

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

Method for integrated circuit fabrication using pitch multiplication

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Pitch reduced patterns relative to photolithography features

A system ( 120 ) detects transmission of potentially unwanted e-mail messages. The system ( 120 ) may receive e-mail messages and generate hash values based on one or more portions of the e-mail messages. The system ( 120 ) may then determine whether the generated hash values match hash values associated with prior e-mail messages. The system ( 120 ) may determine that one of the e-mail messages is a potentially unwanted e-mail message when one or more of the generated hash values associated with the e-mail message match one or more of the hash values associated with the prior e-mail messages.

Hash-based systems and methods for detecting and preventing transmission of unwanted e-mail

A fault-tolerant memory system or "FTMS" is intended for use as mass data storage for a host computer system. The FTMS incorporates a dedicated microprocessor-controlled computer system which serializes blocks of user data as they are received from the host system, deserializes those blocks when they are returned to the host system, implements an error correction code system for the user data blocks, scrubs the data stored in the user memory, remaps data block storage locations within the user memory as initial storage locations therein acquire too may hard errors for error correction to be effected with the stored error correction data, and performs host computer interface operations. Data in the FTMS is not bit-addressable. Instead, serialization of the user data permits bytes to be stored sequentially within the user memory much as they would be stored on a hard disk, with bytes being aligned in the predominant direction of serial bit failure within the off-spec DRAM devices. Such a data storage method facilitates error correction capability.

Method and apparatus for storing digital data in off-specification dynamic random access memory devices

A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Method and apparatus for memory array compressed data testing

A temperature sensing circuit allows a DRAM array to use less power than would normally be possible due to the reduced refresh rate based on the temperature of the DRAM array The temperature circuit removes the refresh guardbanding on the DRAMS Instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAMs every 128 ms is possible, depending on the temperature of the DRAM array

Temperature-dependent DRAM refresh circuit

A flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage. Although the invention was created with field-emission displays in mind, the technique may be used in any matrix-addressable display (e.g. vacuum fluorescent, electro-luminescent, or plasma-type displays) where high pixel activation voltages must be switched. In a preferred embodiment field emission display, emitter-to-grid voltage differential is maintained near zero during non-emission periods, and is raised to a level sufficient to cause emission by grounding pixel emitters at each row and column intersection through a pair of series-connected field-effect transistors (FETs). The emitter base electrode of each emitter node is coupled to the grid via a current-limiting transistor. Display brightness control is accomplished by varying the gate voltages of either FET, such that emission current can be adjusted. In addition, a fusible link is placed in series with the grounding path through the series-connected FETs. Gray scale shading is accompanied by varying the duty cycle of pixel actuation time as a percentage of frame time.

Flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage

A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Random access memory device utilizing a vertically oriented select transistor

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