In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

Dielectric breakdown mechanisms in gate oxides

It has been demonstrated that the introduction of HfO2/ TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This contribution summarizes recent advances in the understanding of charge trapping and defect generation in HfO2/ TiN gate stacks. This paper relates the electrical properties to the chemical/physical properties of the high-epsiv dielectric and discusses test procedures specifically tailored to quantify gate stack reliability of HfO2/TiN gate stacks.

Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks

Electron transport through broken down ultra-thin SiO2 layers in MOS devices

Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection.- Standard and ESD Devices in Integrated Process Technologies.- ESD Clamps.- ESD Network Design Principles.- ESD Design for Signal Path Analog.- Power Management Circuits' ESD Protection.- System-Level and Discrete Components ESD.

/pdf/esd-design-for-analog-circuits-3kiwrw7btq.pdf

ESD Design for Analog Circuits

The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO 2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E a ∼ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V t ) instability ΔI g /I g ∼ dV t 3. Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V t -degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO 2 defects –such as oxygen vacancy – and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V t instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.

Stress-induced leakage current and defect generation in nFETs with HfO 2 /TiN gate stacks during positive-bias temperature stress

The universality of the power-law model for the time to breakdown of thin gate oxides is experimentally established from ldquoDCrdquo down to the ESD regime. This strong gate oxide breakdown voltage acceleration and the cumulative effect of dielectric degradation have severe impacts on the ESD protection development. The statistical aspects of the gate oxide breakdown, its area dependence and the characterization methodology have to be considered for the determination of the ESD design window.

http://ieeexplore.ieee.org/iel5/5235855/5256743/05256767.pdf

Ultra-thin gate oxide reliability in the ESD time domain

Soft breakdown and hard breakdown in ultra-thin oxides

The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.

Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress

Reliability aspects of gate oxide under ESD pulse stress

Influence of gate oxide breakdown on MOSFET device operation

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