Electron-beam inspection (eBI) of the contact (CA) module for silicon-on-insulator (SOI) technology is discussed in this paper. Voltage contrast is used to detect CA opens in the SRAM and both CA opens and shorts in special test structures. The inspection is performed after the tungsten chemical mechanical planarization (W CMP) step. In-line transmission electron microscope (TEM) samples at select defect sites are then prepared and imaged to determine the failure mechanism. This methodology greatly enhances yield learning and provides quick feedback for lithography and etch process adjustments.

Characterization of contact module failure mechanisms for SOI technology using E-beam inspection and in-line TEM

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

Strained Silicon Devices

Silicon-on-insulator (SOI) technology improves the performance of devices by reducing parasitic capacitance. Devices based on SOI or silicon-on-sapphire technology are primarily used in high-performance radio frequency (RF) and radiation sensitive applications as well as for reducing the short channel effects in microelectronic devices. Despite their advantages, the high substrate cost and overheating problems associated with complexities in substrate fabrication as well as the low thermal conductivity of silicon oxide prevent broad applications of this technology. To overcome these challenges, we describe a new approach of using beryllium oxide (BeO). The use of atomic layer deposition (ALD) for producing this material results in lowering the SOI wafer production cost. Furthermore, the use of BeO exhibiting a high thermal conductivity might minimize the self-heating issues. We show that crystalline Si can be grown on ALD BeO and the resultant devices exhibit potential for use in advanced SOI technology applications.

/pdf/advanced-silicon-on-insulator-crystalline-silicon-on-atomic-llr8i5igcc.pdf

Advanced Silicon-on-Insulator: Crystalline Silicon on Atomic Layer Deposited Beryllium Oxide.

L'introduction d'une contrainte mecanique dans le canal de MOSFETs sur SOI est indispensable pour les noeuds technologiques sub-22 nm. Son efficacite depend de la geometrie et des regles de dessin du dispositif. L'impact des etapes du procede de fabrication des transistors (gravure des zones actives, formation de la grille metallique, implantation des Source/Drain (S/D)) sur la contrainte du silicium contraint sur isolant (sSOI) a ete mesure par diffraction des rayons X en incidence rasante (GIXRD). Parallelement, le gain en performances de MOSFETs sur sSOI a ete quantifie par rapport au SOI (100% de gain en mobilite pour des nMOS longs et larges (L=W=10 μm), 35% de gain en courant de drain a saturation (IDsat) pour des nMOS courts et etroits (L=25 nm, W=77 nm)). Des structures contraintes innovantes ont aussi ete etudiees. Un gain en IDsat de 37% (18%) pour des pMOS sur SOI (sSOI) avec des S/D en SiGe est demontre par rapport au sSOI avec des S/D en Si, pour une longueur de grille de 60 nm et des films de 15 nm d'epaisseur. Des mesures GIXRD, couplees a des simulations mecaniques, ont permis d'etudier et d'optimiser des structures originales avec transfert de contrainte d'une couche enterree precontrainte (en SiGe ou en nitrure) vers le canal.

MOSFETs contraints sur SOI : analyse des déformations par diffraction des rayons X et étude des propriétés électriques

The continuous downscaling of the Si-based microelectronics, which is the fundament of today’s information technology, requires novel concepts for the source/drain (S/D) architecture of metal-oxide-semiconductor field-effect transistors (MOSFETs). The improvement of the carrier injection is of prime importance because of the increasing impact of parasitic resistances which strongly limit the performance of ultimately scaled transistors. Moreover, steeper junctions at the contact/channel interfaces become more and more crucial for nanoscale devices. In this context, Schottky-barrier (SB) MOSFETs with metallic S/D are promising performance boosters since they offer low extrinsic resistances and atomically abrupt junctions formed at the metal/silicon interface. However, a drawback of these devices is their performance which is inferior to conventional MOSFETs due to the relatively high Schottky barrier. Recently, dopant segregation has attracted much interest since the highly doped layer formed at the silicide/silicon interface during silicidation strongly improves the tunneling probability of carriers through Schottky contacts. The present thesis studies the integration of NiSi with dopant segregation in SBMOSFETs on thin-body silicon-on-insulator experimentally. The objective of the detailed direct-current (DC) and radio-frequency (RF) characterization is to gain a better insight into the physics of these devices. The modeling of NiSi/p-Si Schottky contacts using a numerical model which combines the thermionic emission theory with image-force induced barrier lowering and quantum-mechanical tunneling provides a solid understanding of the carrier injection of Schottky contacts. The characterization of Schottky diodes with silicidation induced dopant segregation using boron, arsenic and antimony reveals effective Schottky barrier heights in the 0.1 eV regime depending on the implantation dose. Below this value SB-MOSFETs are capable of outperforming conventional MOSFETs. Successfully fabricated longand short-channel pand n-type SB-MOSFETs with and without dopant segregation are characterized performing direct-current (DC) measurements. Transistors with 80 nm channel length reveal on-currents as high as 427μA/μm for p-type and 1150μA/μm for n-type devices, respectively, which compete well with state-of-the-art SB-MOSFETs. For the first time, the extrinsic and intrinsic device parameters of short-channel nand p-type NiSi SB-MOSFETs are extracted using scattering parameter measurements. The radio-frequency (RF) investigation of the devices reveals a perfectly linear scaling and high cut-off frequencies of 140GHz for n-type and 63GHz for p-type SB-MOSFETs with a gate length of 80 nm. The optimization of the reproducible fabrication process improves the S/D resistances by 30% and yields a value of 508Ωμm for devices fabricated on 20 nm thick silicon-on-insulator. Although, the DC performance of SBMOSFETs is strongly deteriorated by high Schottky barriers, it has only a small impact on the cut-off frequency. This can be explained by the similar behavior of the transconductance and the total gate capacitance when the implantation dose and therefore the Schottky barrier height is changed. The benchmarking of the obtained cut-off frequencies with state-of-the-art MOSFETs demonstrates the superior RF performance of the fabricated devices and predicts an impressive performance increase for further downscaling. RF performance limiting parameters are identified and the origin of the RF variability of SB-MOSFETs is discussed. In summary, the results of this work demonstrate a high potential of NiSi S/D SBMOSFETs with dopant segregation for a use in ultimately scaled microelectronics.

DC and RF characterization of NiSi Schottky barrier MOSFETs with dopant segregation

In this paper we present, an overview of partial depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power efficient designs. These techniques have been developed, applied and optimized for 65/45nm volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, High K Metal Gate (HKMG) technology is key. Different HKMG integrations as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

Advanced SOI CMOS transistor technology for high performance microprocessors

In this paper we present an overview of partially depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power-efficient designs. These techniques have been developed, applied and optimized for 45 nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32 nm design rules, High K Metal Gate (HKMG) technology is the key. Different HKMG integrations as well as future strained Si technologies, like strained silicon directly bonded on SOI, and embedded Si:C are discussed.

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Advanced SOI CMOS transistor technology for high performance microprocessors

Advanced SOI CMOS transistor technology for high performance microprocessors