A completion-detection method is proposed for efficiently implementing Boolean functions as self-timed logic structures. Current-sensing completion detection (CSCD) allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: reduced parasitic capacitance, removal of spacer tokens in the data stream, and computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison. >

Self-timed logic using current-sensing completion detection (CSCD)

This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: (1) reduced parasitic capacitance, (2) removal of spacer tokens in the data stream, and (3) computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison.

Self-timed logic using Current-Sensing Completion Detection (CSCD)

Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Data transmitting device, data receiving device, data transmitting system, and data transmitting method

The purpose of this book is to present a current view of the state of the art for the field of asynchronous circuit design and analysis which was the topic of a workshop in Banff in the fall of 1993. Asynchronous circuits have been studied in one form or another since the early 1950’s [64] when the focus was primarily on mechanical relay circuits and when the differences between the asynchronous and clocked circuit design styles were somewhat indistinct. A number of theoretical issues were studied in detail by Muller and Bartky as early as 1956 [92]. Since then, the field of asynchronous circuits has gone through a number of high-interest cycles. In the last 5 years there has been an unprecedented level of interest in both academic and industrial settings [56]. This historical trend continues today with the majority of the current research effort focused more on theory than on practice. Nonetheless, the advance of practical asynchronous circuit design techniques also has an unusual level of interest. The work presented at the Banff workshop was concerned more with practice than theory and provided a reasonable coverage of the current approaches to asynchronous circuit design. Similarly this chapter will primarily focus on practical design issues. Prior to introducing the four chapters which follow, we present an introduction to the basic concepts and motivations behind asynchronous circuit design. This will hopefully enable those not already familiar with asynchronous circuit design to better understand the subsequent chapters.

Asynchronous Circuit Design: Motivation, Background, & Methods

Delay-insensitive dual-rail and bundled data design methodologies are the two main approaches used for the creation of asynchronous circuits. Bundled data allows the creation of fast, low overhead circuits, whereas dual-rail allows bit-level pipelining and average case performance. This paper describes 'Early output' logic, which combines the positive features of the two methods to create faster asynchronous circuits. This method allows the creation of circuits yielding performance faster than their synchronous counterparts. Early output implementations allow logic to evaluate results before all inputs are presented. The results move to the next stage, but the current stage stalls while waiting for the late inputs to arrive simply to acknowledge them. This unnecessary wait can be removed by allowing backwards propagating 'Anti-Tokens' to remove the late inputs. The use of anti-tokens and improved semi-decoupled latches allows the removal of many stalls due to unnecessary synchronisations, thus improving the performance of the circuit.

Early Output Logic using Anti-Tokens

Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)

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Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)