Tae-Woo Kim
University of Ulsan
133 Papers
552 Citations
Tae-Woo Kim is an academic researcher from University of Ulsan. The author has contributed to research in topics: High-electron-mobility transistor & MOSFET. The author has an hindex of 17, co-authored 110 publications. Previous affiliations of Tae-Woo Kim include Sejong University & Gwangju Institute of Science and Technology.
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Papers
Lg = 100 nm In0.7Ga0.3As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer
Donghyi Koh,Donghyi Koh,Hyuk-Min Kwon,Tae-Woo Kim,Dae-Hyun Kim,Dae-Hyun Kim,Todd W. Hudnall,Christopher W. Bielawski,W. Maszara,Dmitry Veksler,David Gilmer,Paul Kirsch,Sanjay K. Banerjee +12 more
TL;DR: In this paper, the authors have fabricated nanometer-scale channel length quantum-well (QW) MOSFETs incorporating beryllium oxide (BeO) as an interfacial layer.
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A Capless $hboxInP/hboxIn_0.52hboxAl_0.48hboxAs/hboxIn_0.53hboxGa_0.47hboxAs$ p-HEMT Having a Self-Aligned Gate Structure
TL;DR: In this article, a 0.2mum capless InAlAs/InGaAs pseudomorphic high electron mobility transistor (p-HEMT) with a self-aligned gate (SAG) was investigated.
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Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of $\hbox{In}_{0.52}\hbox{Al}_{0.48}\hbox{As/In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ p-HEMTs
Tae-Woo Kim,Dae-Hyun Kim,Sang Park Duk,Geun Yeom Young,Byeong Lim Ok,Jin-Koo Rhee,Jae-Hyung Jang,Jong-In Song +7 more
TL;DR: In this article, the characteristics of 0.15-mum InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based ALET technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated.
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Challenges of III–V materials in advanced CMOS logic
Paul Kirsch,Hill Richard J,Jiacheng Huang,Wei-Yip Loh,Tae-Woo Kim,Man Hoi Wong,B.-G. Min,Craig Huffman,Dmitry Veksler,Chadwin D. Young,K.-W. Ang,I. Ali,Rinus T. P. Lee,T. Ngai,A. Wang,W.-E Wang,T.H. Cunningham,Y.T. Chen,P. Y. Hung,E. Bersch,B. Sassman,M. Cruz,S. Trammell,Ravi Droopad,S. Oktybrysky,J.C. Lee,Gennadi Bersuker,Chris Hobbs,R. Jammy +28 more
- 23 Apr 2012
TL;DR: This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj;60;10nm.
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