Japanese journal of applied physics : JJAP online.

An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

Semiconductor device and electronic device

A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.

Semiconductor device and method for driving semiconductor device

Thin-film transistors for large-area electronics

This chapter is a white paper describing a platform for scaled-up neuromorphic systems to ‘human brain size’ complexity. Such a system will be necessary for massive search and analysis tasks while interacting with biological data. This system would consist of similar number of neurons and synapses as in an adult human brain. One of the largest bottlenecks is the huge synaptic complexity that would result from connecting billions of neurons. The purpose of this chapter is to describe a feasible architecture that could handle the enormous communication bandwidth necessary for such a large-scale neuromorphic system. The proposed approach is grounded in the assumption that we would only be able to appreciate the utility of a neuromorphic system when it is somewhat similar to the human brain in terms of energy consumption and size. Inspired by the recent advancements in SoC architecture, a novel scalable intercluster communication network is proposed here. A particularly useful instantiation of this occurs for the global synaptic communication, interconnecting the local clusters of synapse arrays. The core of the proposed solution is a novel switching architecture in the CMOS back end of line (BEOL) that is expected to be extremely power efficient. In contrast to a fixed predefined bus that is shared over all connected local clusters, the proposed solution will allow a multitude of dedicated point-to-point connections that can be switched dynamically.

Very Large-Scale Neuromorphic Systems for Biological Signal Processing

A processor having a power management unit (PMU) and an 8-bit CPU including flip-flops with shadow memories is fabricated by 0.5-μm Si and 0.8-μm c-axis-aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO) technology. The shadow memories hold data without power supply utilizing low off-state current of CAAC-IGZO FETs. A break-even time (BET) of 4.9μs has been obtained. Good scalability of the processor in writing data to shadow memories and in area (5.7% overhead or less) is also confirmed through simulation and layout, based on flip-flops using 30-nm Si FETs combined with 0.3-μm CAAC-IGZO FETs which show good electronic characteristics and no overhead in area.

Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor

Eight-bit CPU with Nonvolatile Registers Capable of Holding Data for 40 Days at 85°C Using Crystalline In-Ga-Zn Oxide Thin Film Transistors

A state retention flip flop which retains its state without power, has zero area overhead, a theoretical zero backup time and simple power control is demonstrated in a Normally-Off 32-bit CPU.

Zero Area Overhead State Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Thin Film Transistor with Simple Power Control Implemented in a 32-bit CPU

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Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor

Eight-bit CPU with Nonvolatile Registers Capable of Holding Data for 40 Days at 85°C Using Crystalline In-Ga-Zn Oxide Thin Film Transistors

Zero Area Overhead State Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Thin Film Transistor with Simple Power Control Implemented in a 32-bit CPU