High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

High-Density Through Silicon Vias for 3-D LSIs

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chem- ical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

High-Density Through Silicon Vias for 3-D LSIs : Silicon stacked chips that perform highly-parallel data transfer have been successfully fabricated for image processing, artificial retinas, and for microprocessor and memory testing

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

We succeeded in developing high-speed electrodeposition and high-rate CMP processes that greatly reduced the cost of Cu through-via fabrication used for three-dimensional (3D) chip stacking. Thin-wafer-handling processes were integrated with the development of wafer bonding and debonding equipment and processes. The investigation of thermal characteristics revealed the important structural guidelines for heat dissipation. Finally, the difficult challenges of 3D chip stacking, cost issues, wafer-handling issues and thermal issues, as well as fine pitch interconnection and electrical performance evaluation, have been established. Part of the achievements were applied to practical use in a commercial application.

Process integration of 3D chip stack with vertical interconnection

Tire pressure monitoring systems (TPMS) are beneficial for the environment and road and passenger safety. Miniaturizing the TPMS allows sensing of additional parameters. This paper presents a miniaturized TPMS with a volume less than 1 cm3, realised by 3D stacking and through-silicon via (TSV) technology. Suitable technologies with low electrical resistance and high bond strengths were evaluated for stacking the microcontroller, transceiver, pressure sensor and bulk acoustic resonator (BAR) in the TPMS. 60 μm deep W-filled TSVs with resistance 0.45 Ω and SnAg micro bumps with a bond strength of 53 MPa were used for stacking the transceiver to the microcontroller. TSVs through the whole wafer thickness with resistance 6 Ω were used for the pressure sensor. Au stud bumps were used for stacking the pressure sensor and BAR devices. The final TPMS stack was packaged in a moulded interconnect device (MID) package.

Miniaturised Sensor Node for Tire Pressure Monitoring (e-CUBES)

Y. Igarashi, T. Morooka, Y. Yamada, T. Nakamura, K.W. Leel, ICT. park, H. Kurino and M. Koyanagr DepL ofMachine lntelligence and Systems Engineering, 'Ibhoku Univ. 0l Aza-Ararnaki, Aoba-ku, Sendei 98G8579, Japan Phone: +81-22-217{909; E-Mail: sdlab(Asd.mech.tohoku.acjp rJST(Japan Science and Technolo$/ Corporation)

Filling of Tungsten into Deep Trench Using Time-Modulation CVD Method

l.Introduction Three-Dimensional (3D) integration is the most promising technology to improve the LSI performance by reducing the wiring delay and increasing the interconnection density. However, 3D LSI has a concern of increasing heat accumulation as a result of vertically stacking many chips and isolating them with insulating materials with low thermal conductivity. Several works about the heat generation and accumulation in 3D LSI have been reported so farl'2. However, these works describe mainly the results obtained by the computer simulation. In this work, we evaluate the heat generation and accumulation in 3D LSI by directly measuring the chip temperature using fabricated 3D LSI test chips. Furthermore, we compare the experimental results with those obtained by the simulation to reveal the mechanism of thermal flow in 3D LSI.

Thermal Analysis of Self-Heating Effect in Three Dimensional LSI

This paper presents a wafer-level stacking technology with vertical interconnections for 3-dimensional (3-D) microsystems. Several thinned chips, which are composed of homo or heterogeneous devices and systems, are vertically stacked and electrically interconnected with more than 105 precise and short vertical wires formed through the chips. Deep Si trench-holes filled with low-resistance P-doped poly-Si and Au/In micro-bumps were used for the vertical interconnections between chips. An 8×8 pixels 3-D stacked CMOS image sensor was fabricated and successfully demonstrated its functions.

A 3-Dimensional Wafer-Level Stacking Technology with Precise Vertical Interconnections to MEMS Applications

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Papers

Filling of Tungsten into Deep Trench Using Time-Modulation CVD Method

Thermal Analysis of Self-Heating Effect in Three Dimensional LSI

A 3-Dimensional Wafer-Level Stacking Technology with Precise Vertical Interconnections to MEMS Applications