Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Methods for forming a transistor and modulating channel stress

The harmonic distortion (HD) exhibited by unstrained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin. The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

Strain evaluation in a small area is required because the extremely short channel length in state-of-the-art metal–oxide–semiconductor field-effect transistors (MOSFETs) leads to a narrow and shallow channel region. The strain in this limited area strongly affects the device performance owing to carrier mobility modification. We used UV–Raman spectroscopy with a quasi-line-shape excitation source and a two-dimensional charge-coupled-device detector in order to evaluate the strain distribution in Si or Si-on-insulator (SOI) substrates with a patterned SiNx film. As results, the strain was concentrated at the SiNx/Si interface and SiNx film pattern edge. A large tensile (compressive) strain was induced by the SiNx film with inner tensile (compressive) stress in the space region that corresponds to a channel region of the n- or p-MOSFETs. We assume that these large strains in the space region are the origin of the mobility enhancement in n- or p-MOSFETs. Furthermore, in addition to the size effect of channel length, we confirmed that the strain could be controlled by changing SiNx film thickness, film stress, and the substrate (SOI or bulk-Si). The quantitative evaluation of strain by means of simulation is also discussed.

Characterization of Strain for High-Performance Metal–Oxide–Semiconductor Field-Effect-Transistor

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

“Strained-Si”, in which intentional strain is introduced in Si crystal to improve carrier mobility by using a modulated band structure, is recognized as one of the most important technologies in post-scaling-generation LSIs. Strain-evaluation technology to probe strain in shallow surfaces that correspond to the channels of MOSFETs is crucial to achieving strained-Si technology. In this paper, we introduce the results we obtained by evaluating strain with the new UV-Raman spectroscopy we developed. Quasi-line shape illumination enabled Raman measurements with 200-nm intervals on the sample. The local-strain mechanism caused by SiN stressors covering a MOSFET was clarified by measuring one-dimensional strain profiles induced by patterned SiN film on Si. We also demonstrated that the induced strain was proportional to the inner stresses of SiN film and that it is more effective to introduce strain in SOI substrates than in bulk substrates. In the evaluation of a actual device fabricated by using the gate-last process in which strain was significantly enhanced after the dummy gate was removed, the size effect, i.e., an increase in induced strain with a decrease in gate length, was confirmed through one-dimensional strain-profile measurements with various gate lengths.

Evaluation of local strain in Si using UV-Raman spectroscopy

We study the effects of a strained contact etch stop layer (CESL) on fully depleted (FD) silicon-on-insulator (SOI) devices with ultra thin silicon channels. As expected from extensive simulation analysis, the electrical results demonstrate that in spite of the raised source/drain architecture, the stress is effectively transferred from the liner into the underlying channel. Using a tensile liner for the n-type metal–oxide–semiconductor field effect transistor (nMOS) and a compressive liner for the p-type metal–oxide–semiconductor field effect transistor (pMOS), transistor performance enhancements of 10% and 17%, respectively, were obtained. Moreover, with a tensile (/compressive) liner, tensile (/compressive) edge effects become dominant for short devices whereas the stress becomes less tensile (/compressive) for longer devices. Indeed, the balance between these two contributions and the strain level in the channel are highly dependent on geometrical parameters (W, Lgate).

Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

Effect of Process Induced Strain in 35 nm FDSOI Devices with Ultra-Thin Silicon Channels

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Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

Effect of Process Induced Strain in 35 nm FDSOI Devices with Ultra-Thin Silicon Channels