A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.

/pdf/1-25-gb-s-regulated-cascode-cmos-transimpedance-amplifier-2q3qbswozq.pdf

1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and has proven quite challenging. We review some of the work in this field with the goal of informing the reader as to the origin of the challenges and the implementation tradeoffs. Finally, we report experimental results from a monolithic CMOS photoreceiver realized in a 0.35-/spl mu/m production CMOS process, including a CMOS photodiode. Operating at 1 Gb/s, the receiver requires an average input power of -6.3 dBm at 850 nm to obtain a measured bit error rate of 1/spl times/10/sup -9/, and dissipates 1.5 mW at 2.2 V, increasing to 6 mW at 3.3 V.

1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies

A new and innovative interconnection technology applicable for printed circuit boards is presented. This technology is widely compatible with the existing design and manufacturing processes and technologies for conventional multilayer pc boards and it combines electrical and optical interconnects on pc board level. It provides the potential for on-board bandwidth of several Gb/s and closes the bottleneck caused by the limited performance of electrical interconnection technology. After giving an overview on the most important basic technologies and first available results and engineering samples, the focus of this paper is on the development of appropriate modeling methodologies and simulation algorithms necessary for designing and optimizing optical on-board interconnects within the conventional electrical pc board environment.

A high-performance hybrid electrical-optical interconnection technology for high-speed electronic systems

A method of fabricating light-sensing devices including photodiodes monolithically integrated with CMOS devices. Several types of photodiode devices (PIN, HIP) are epitaxially grown in one single step on active areas implanted in a common semiconductor substrate, the active areas having defined polarities. The epitaxially grown layers for the photodiode devices may be either undoped or in-situ doped with profiles suitable for their respective operation. With appropriate choice of substrate materials, device layers and heterojunction engineering and process architecture, it is possible to fabricate silicon­based and germanium-based multi-spectral sensors that can deliver pixel density and cost of fabrication comparable to the state of the art CCDs and CMOS image sensors. The method can be implemented with epitaxially deposited films on the following substrates: Silicon Bulk, Thick-Film and Thin-Film Silicon-On-Insulator (SOI), Germanium Bulk, Thick-Film and Thin-Film Germanium-On-Insulator (GeOI).

Light-sensing device

Results of optoelectronic integrated CMOS receivers for applications in optical data transmission and in optical interconnects are presented. The rise and fall times of the integrated p-i-n photodiodes (PDs) are 0.19 and 0.24 ns, respectively, corresponding to -3 dB bandwidths in excess of 1.4 GHz. These PDs combine this high speed with a high quantum efficiency. Rise and fall times of 0.53 and 0.69 ns, respectively, are obtained for CMOS optoelectronic integrated circuits (OEICs) with integrated p-i-n PD's. These OEICs in 1.0 /spl mu/m CMOS technology handle a data rate of 622 Mb/s with a single-supply voltage of 3.3 V.

Monolithic high-speed CMOS-photoreceiver

Results of a monolithically integrated Si optical receiver for applications in optical data transmission and in optical interconnects with wavelengths of 638 and 850 nm are presented. The optoelectronic integrated circuit (OEIC) implementing a vertical p-type-intrinsic-n-type photodiode achieves a data rate of 1 Gb/s for 638 nm with a sensitivity of -15.4 dBm at a bit-error rate of 10/sup -9/. The sensitivity of this OEIC in a 1.0-/spl mu/m CMOS technology is improved by at least a factor of four compared to that of published submicrometer OEICs. A 25-THz./spl Omega/ effective transimpedance bandwidth product of the implemented amplifier is achieved.

A monolithically integrated 1-Gb/s optical receiver in 1-μm CMOS technology

Results of new CMOS-integrated PIN photodiodes in optoelectronic integrated circuits (OEICs) for applications in optical storage systems, in optical data transmission and in optical interconnects are presented. The rise and fall times of the integrated PIN photodiodes are below 0.3 us. The CMOS-integrated PIN photodiodes are sufficient for a NRZ data rate of 1.5 Gb/s and the results show that PIN CMOS receiver OEICs in submicron technologies enable data rates up to 1 Gb/s. These photodiodes combine this high speed with a high quantum efficiency of approximately 50%. The further improvement of their quantum efficiency above 90% by the integration of an antireflection coating is discussed. Low-offset PIN-CMOS-OEICs for application in digital-versatile-disk (DVD) systems with bandwidths in excess of 32 MHz are presented. A high speed PIN-CMOS-OEIC in 1.0 /spl mu/m technology for optical data transmission exhibits a data rate of 622 Mb/s.

Advanced photo integrated circuits in CMOS technology

A new double photodiode requiring no' process modifications in CMOS and BiC­ MOS technologies is shown to achieve a bandwidth in excess of 360 MHz and data rates exceeding 622 Mb/s. Furthermore, an innovative PIN photodiode requiring only one additional mask for the integration in a CMOS process is shown to be capable of handling a data rate of 1.1 Gb/s.

http://ieeexplore.ieee.org/iel5/10061/32274/01505507.pdf

Integrated High-speed, High-responsivity Photodiodes in CMOS and BiCMOS Technology

A new BiCMOS OEIC for advanced optical storage systems with enhanced bandwidths is presented. The photodiode and the amplifier are monolithically integrated on the same substrate of a standard BiCMOS process. The OEIC has a -3 dB-bandwidth of 147 MHz. Furthermore a monolithically integrated pin-photoreceiver in CMOS-technology capable of 622 Mbit/s at a single power supply of only 2.5V is introduced.

http://ieeexplore.ieee.org/iel5/9918/31527/01471180.pdf

Advanced CMOS and BiCMOS photonic receiver ICs

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