T. Eimori
Renesas Electronics
24 Papers
289 Citations
T. Eimori is an academic researcher from Renesas Electronics. The author has contributed to research in topics: Metal gate & High-κ dielectric. The author has an hindex of 9, co-authored 24 publications.
Chat about Author
Papers
Discrete Dopant Effects on Statistical Variation of Random Telegraph Signal Magnitude
TL;DR: In this paper, the discrete channel dopant effects on the statistical variation of random telegraph signal (RTS) magnitude, defined by the threshold-voltage shift by RTS in MOSFETs, were discussed.
112
Patent
Wire structure, semiconductor device, MRAM, and manufacturing method of semiconductor device
T. Eimori
- 13 Oct 2005
TL;DR: In this article, a wire structure is provided in an insulating film formed on a base, where a trench is formed in the surface of the film, and a plurality of carbon nanotubes are included in this trench.
34
Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects
Motoyuki Sato,Naoto Umezawa,J. Shimokawa,Hiroaki Arimura,Shinya Sugino,A. Tachibana,M. Nakamura,Nobuyuki Mise,S. Kamiyama,Tetsu Morooka,T. Eimori,Kenji Shiraishi,Kikuo Yamabe,Heiji Watanabe,Kizuku Yamada,T. Aoyama,Toshihide Nabatame,Yasuo Nara,Yuzuru Ohji +18 more
- 01 Dec 2008
TL;DR: In this article, the authors clarified the impact on reliability of La incorporation into the HfSiON gate dielectrics nMOSFETs (PBTI, TDDB).
27
Patent
Semiconductor device which has mos structure and method of manufacturing the same
Hidekazu Oda,T. Eimori,J. Yugami,Takahiro Maruyama,Tomohiro Yamashita,Y. Nishida,S. Yamanari,T. Hayashi,Kenichi Mori +8 more
- 03 Jul 2006
TL;DR: In this article, the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.
19
Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond
M. Ishibashi,Katsuyuki Horita,Mahito Sawada,Masashi Kitazawa,Motoshige Igarashi,T. Kuroi,T. Eimori,Kiyoteru Kobayashi,M. Inuishi,Yuzuru Ohji +9 more
TL;DR: In this paper, a shallow trench isolation (STI) process is proposed for 45 nm node technologies and beyond using a fluorine-doped SiO2 film for gap filling and high temperature rapid thermal oxidation (HT-RTO) for gate oxidation.
17