The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >

Recent advances in VLSI layout

The authors propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. The approach is based on a new bounded-radius minimum routing tree formulation. The authors first present several heuristics with good performance, based on an analog of Prim's minimum spanning tree construction. Next, they give an algorithm which simultaneously minimizes both routing cost and the longest interconnection path, so that both are bounded by small constant factors away from optimal. They also show that geometry helps in routing: in the Manhattan plane, the total wire length for Steiner routing improves to 3/2*(1+(1/ epsilon )) times the optimal Steiner tree cost, while in the Euclidean plane, the total cost is further reduced to (2/ square root 3)*(1+(1/ epsilon )) times optimal. The method generalizes to the case where varying wire length bounds are prescribed for different source-sink paths. Extensive simulations confirm that this approach works well. >

/pdf/provably-good-performance-driven-global-routing-3dzyyynxs5.pdf

Provably good performance-driven global routing

List of Figures. List of Tables. 1: Preliminaries. 1.1. Preface. 1.2. The Domain of Discourse: Routing in VLSI Physical Design. 1.3. Overview of the Book. 1.4. Acknowledgements. 2: Area. 2.1. Introduction. 2.2. Performance Bounds for MST-Based Strategies. 2.3. Iterated 1-Steiner (I1S). 2.4. Enhancing I1S Performance. 2.5. Practical Implementation Options for I1S. 2.6. On the Maximum MST Degree. 2.7. Steiner Trees in Graphs. 3: Delay. 3.1. Preliminaries. 3.2. Geometric Approaches to Delay Minimization. 3.3. Minimization of Actual Delay. 3.4. New Directions. 4: Skew. 4.1. Preliminaries. 4.2. An Early Matching-Based Approach. 4.3. DME: Exact Zero Skew with Minimum Wirelength. 4.4. Planar-Embeddable Trees. 4.5. Remarks. 5: Multiple Objectives. 5.1. Minimum Density Trees. 5.2. Multi-Weighted Graphs. 5.3. Prescribed-Width Routing. A: Appendix: Signal Delay Estimators. A.1. Basics. A.2. Accuracy and Fidelity. References. Author Index. Term Index.

On optimal interconnections for VLSI

An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm. This technique is dependent solely upon the interconnect topology and the direction of signal flows between cells and nets. The formulation of cell gains is extended to model the effect of cell replication, and the necessary modifications to the algorithm are described. >

A cell-replicating approach to minicut-based circuit partitioning

The authors point out that minimizing clock skew is important in the design of high-performance VLSI systems. A general clock routing scheme that achieves extremely small clock skews while still using a reasonable amount of wirelength is presented. The routing solution is based on the construction of a binary tree using geometric matching. For cell-based designs, the total wirelength of the clock routing tree is on average within a constant factor of the wirelength in an optimal Steiner tree, and in the worst case is bounded by O( square root l/sub 1/l/sub 2/*1 square root n) for n terminals arbitrarily distributed in the l/sub 1/*l/sub 2/ grid. The bottom-up construction readily extends to general cell layouts, where it also achieves essentially zero clock skew within reasonably bounded total wirelength. The algorithms have been tested on numerous random examples and also on layouts of industrial benchmark circuits. The results are very promising: the clock routing yields near-zero average clock skew while using total wirelength competitive with that used by previously known methods. >

/pdf/matching-based-methods-for-high-performance-clock-routing-1qrq75t1uv.pdf

Matching-based methods for high-performance clock routing

We present a new routing region definition and ordering (RRDO) scheme for building block layout. Given an arbitrary placement of rectangular blocks (including the case with cycles in the channel precedence constraints), without modifying the placement, our scheme defines and orders channels so that when a new channel is being routed, its width can be expanded or contracted without destroying the previously routed channels. The cycles in the channel precedence constraints are broken by introducing a new kind of channel--the L-shaped channels. Unlike switchboxes, L-shaped channels can be expanded or contracted to permit the completion of routing without rerouting other existing channels. An efficient greedy RRDO algorithm has been implemented, which tries to generate as few L-shaped channels as possible since L-shaped channels are harder to route than straight channels. Our algorithm represents routing regions by a floor plan graph, for which we provide a precise definition and a construction algorithm. The experimental results of the RRDO algorithm are promising.

Routing Region Definition and Ordering Scheme for Building-Block Layout

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

T. Asano

Author Tools

Chat about Author

Papers

Routing Region Definition and Ordering Scheme for Building-Block Layout