INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY STABILIZATION OF SUB GRADE SOIL BY USING FOUNDRY SAND WASTE Prashant Kumar, Prof. M.C.Paliwal, Prof. A.K.Jain M .Tech. Scholar (Civil),Department of Civil and Environment Engineering, NITTTR,Bhopal, India Associate Professor,Department of Civil and Environment Engineering, NITTTR,Bhopal, India Professor, Department of Civil and Environment Engineering, NITTTR,Bhopal, India

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International journal of engineering sciences & research technology

In the VLSI physical design, floorplanning is an essential design step, as it determines the size, shape, and locations of modules in a chip and as such it estimates the total chip area, the interconnects, and, delay. Computationally, VLSI floorplanning is an NP hard problem. So many researchers have suggested various heuristics and metaheuristic algorithms to solve the VLSI floorplan problem. The representation of floorplan is an important aspect of the floorplanning Stage. The floorplan representations have an important impact on the complexity and search space of the floorplan design. In this paper, we included studying and comparing PSO, SA and ACO as optimization algorithms for floorplanning and the representations involved in the VLSI floorplanning problem.

A review on VLSI floorplanning optimization using metaheuristic algorithms

Automated floorplanning or space layout planning has been a long-standing NP-hard problem in the field of computer-aided design, with applications in integrated circuits, architecture, urbanism, and operational research. In this paper, we introduce GenFloor, an interactive design system that takes geometrical, topological, and performance goals and constraints as input and provides optimized spatial design solutions as output. As part of our work, we propose three novel permutation methods for existing space layout graph representations, namely O-Tree and B∗-Tree representations. We implement our proposed floorplanning methods as a package for Dynamo, a visual programming tool, with a custom GUI and additional evaluation functionalities to facilitate designers in their generative design workflow. Furthermore, we illustrate the performance of GenFloor in two sets of case-study experiments for residential floorplanning tasks by (a) measuring the ability of the proposed system to find a known optimal solution, and (b) observing how the system can generate diverse floorplans while addressing given a constant residential design problem. Our results indicate that convergence to the global optimum is achieved while offering a diverse set of solutions of a residential floorplan corresponding to local optimums of the solution landscape.

GenFloor: Interactive generative space layout system via encoded tree graphs

Spatial computing experiences are physically constrained by the geometry and semantics of the local user environment. This limitation is elevated in remote multi-user interaction scenarios, where finding a common virtual ground physically accessible for all participants becomes challenging. Locating a common accessible virtual ground is difficult for the users themselves, particularly if they are not aware of the spatial properties of other participants. In this paper, we introduce a framework to generate an optimal mutual virtual space for a multi-user interaction setting where remote users' room spaces can have different layout and sizes. The framework further recommends movement of surrounding furniture objects that expand the size of the mutual space with minimal physical effort. Finally, we demonstrate the performance of our solution on real-world datasets and also a real HoloLens application. Results show the proposed algorithm can effectively discover optimal shareable space for multi-user virtual interaction and hence facilitate remote spatial computing communication in various collaborative workflows.

Optimization and Manipulation of Contextual Mutual Spaces for Multi-User Virtual and Augmented Reality Interaction.

In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally, it is a NP hard problem. So many researchers from time to time have suggested various heuristics and metaheuristic approaches for solving the VLSI Floorplan Problem. The Floorplan representation is another important aspect of the Floorplanning Stage. Representations have a great impact on the complexity of the Floorplan design. In this paper, we survey the VLSI Floorplanning problem which includes studying and comparing the different optimization algorithms and the representations involved in the VLSI Floorplanning problem. Additionally we suggest some of the new approaches for solving the floorplanning problem which has not yet been employed in this regard.

A survey on VLSI Floorplanning: Its representation and modern approaches of optimization

Floorplanning is an essential design step for hierarchical building module design methodology. Floorplanning provides early feedback that evaluates architectural decisions, estimates chip area, estimates delay and congestion caused by wiring. As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchical design and Intellectual Property modules are widely used. This makes floorplanning much more critical to the quality of a Very Large Scale Integration (VLSI) design. For many years, floorplanning is a critical step, as it sets up the ground work for a layout. However, it is computationally quite hard. The process of determining block shapes and positions with area minimization objective and aspect ratio requirement is referred to as floorplanning. Common strategy for blocks floorplanning is to determine in the first phase and then the relative location of the blocks to each other based on connection-cost criteria. In the second step, block sizing is performed with the goal of minimizing the overall chip area and the location of each block is finalized. From the computational point of view, VLSI floorplanning is NP-hard. The solution space will increase exponentially with the growth of circuits scale, thus it is difficult to find the optimal solution by exploring the global solution space. To handle this complexity swarm based optimization method has opted in this proposed work. A generalize solution has developed to take care of area as well as interconnection wire length. To achieve this weighted objective function has defined. The advantages of PSO like simplicity in implementation, not depends upon the characteristics of objective function and better performance have given support to include it as a solution method. Physical design begins with a floorplan. The floorplan estimates the area of major units in the chip and defines their relative placements. The floorplan is essential to determine whether a proposed design will fit in the chip area budgeted and to estimate wiring lengths and wiring congestion, so an initial floorplan should be prepared as soon as the logic is loosely defined. Based on the area of the design and the hierarchy, a suitable floorplan is decided upon. Floorplanning takes into account the macros used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design. Floorplanning also decides the IO structure, aspect ratio of the design. A bad floorplan will lead to wastage of die area and routing congestion. To overcome the problem of floorplanning an automated system which taken the input as DFG by the technological help of the PSO has been defined. The problem of the floorplanning has been transferred as a problem of constraint optimization to take care of non overlapping requirement. The purposed method is not only taking care of required area for the floorplanning but also how to minimize the interconnected wire length is also involved. By considering the following constraints such as:  Non overlapping constraint: No two modules should overlap.  Wire length estimation: Wire length between two modules is calculated by calculating the distance between centers of two modules.  Area Estimation: It's the area of rectangle of minimum size, enclosing all the blocks.  Cost Function & Constraints: A floorplan has an area cost, i.e., which is measured by the area of the smallest rectangle enclosing all the modules and an interconnection cost, i.e., Wire length, which is the total length of the wires fulfilling the interconnections between the modules.

Minimization of Floorplanning Area and Wire Length Interconnection Using Particle Swarm Optimization

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Minimization of Floorplanning Area and Wire Length Interconnection Using Particle Swarm Optimization