A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.

System, method, and computer program product for improving memory systems

Recent trends of CMOS technology scaling and wide-spread use of multicore processors have dramatically increased the power consumption of main memory. It has been estimated that modern data-centres spend more than 30% of their total power consumption in main memory alone. This excessive power dissipation has created the problem of 'memory power wall' which has emerged as a major design constraint inhibiting further performance scaling. Recently, several techniques have been proposed to address this issue. The focus of this paper is to survey several architectural techniques designed for improving power efficiency of main memory systems, specifically DRAM systems. To help the reader in gaining insights into the similarities and differences between the techniques, this paper also presents a classification of the techniques on the basis of their characteristics. The aim of this paper is to equip the engineers and architects with knowledge of the state of the art DRAM power saving techniques and motivate them to design novel solutions for addressing the challenges presented by the memory power wall problem.

/pdf/a-survey-of-architectural-techniques-for-dram-power-27yzrfkyn5.pdf

A survey of architectural techniques for DRAM power management

Energy efficiency is the major optimization criterion for systems-on-chip (SoCs) for mobile devices (smartphones and tablets). Through silicon via (TSV) technology enables 3-D integration of dies and the heterogeneous stacking of multiple memory or logic layers, allowing increased bandwidth and lower energy consumption of the memory interface compared to traditional approaches. In this paper, we explore the 3-D-DRAM architecture design space. The result is an optimized 2 Gb 3-D-DRAM, which shows a 83% lower energy/bit than a 2 Gb device. Furthermore, we propose a highly energy-efficient DRAM subsystem for next-generation 3-D-integrated SoCs, consisting of a SDR/DDR 3-D-DRAM controller and an attached 3-D-DRAM cube with fine-grained access and a flexible (WIDE-IO) interface. We assess the energy efficiency using a synthesizable model of the SDR/DDR 3-D-DRAM channel controller (CC) as well as functional models of the 3-D-stacked DRAM, including an accurate power estimation engine. We also investigate different DRAM families (WIDE IO SDR/DDR, LPDDR, and LPDDR2) and densities from 256 Mb to 4 Gb per channel. The implementation results of the proposed 3-D-DRAM subsystem show that energy optimized accesses to the 3-D-DRAM enable up to 50% energy savings compared to standard accesses. To the best of our knowledge this is the first design space exploration for 3-D-stacked DRAM considering different technologies based on real-world physical data and the first design of a 3-D-DRAM CC and 3-D-DRAM model featuring co-optimization of memory and controller architecture.

Exploration and Optimization of 3-D Integrated DRAM Subsystems

Communications systems make heavy use of FPGAs; their programmability allows system designers to keep up with emerging protocols and their high-speed transceivers enable high bandwidth designs. While FPGAs are extensively used for packet parsing, inspection and classification, they have seen less use as the switch fabric between network ports. However, recent work has proposed embedding a network-on-chip (NoC) as a new “hard” resource on FPGAs and we show that by properly leveraging such a NoC one can create a very efficient yet still highly programmable network switch. We compare a NoC-based 16×16 network switch for 10-Gigabit Ethernet traffic to a recent innovative FPGA-based switch fabric design. The NoC-based switch not only consumes 5.8× less logic area, but also reduces latency by 8.1× We also show that using the FPGA's programmable interconnect to adjust the packet injection points into the NoC leads to significant performance improvements. A routing algorithm tailored to this application is shown to further improve switch performance and scalability. Overall, we show that an FPGA with a low-cost hard 64-node mesh NoC with 64-bit links can support a 16 × 16 switch with up to 948 Gbps in aggregate bandwidth, roughly matching the transceiver bandwidth on the latest FPGAs.

/pdf/efficient-and-programmable-ethernet-switching-with-a-noc-4u6u0ztfyc.pdf

Efficient and programmable ethernet switching with a NoC-enhanced FPGA

In today's datacenters handling big data and for exascale computers of tomorrow, there is a pressing need for high-radix switches to economically and efficiently unify the computing and storage resources that are dispersed across multiple racks. In this paper, we present SCOC, a switch architecture suitable for economical IC implementation that can efficiently replace crossbars for high-radix switch nodes. SCOC is a multi-stage bufferless network with O(N2/m) cost, where m is a design parameter, practically ranging between 4–16. We identify and resolve more than five fairness violations that are pertinent to hierarchical scheduling. Effectively, from a performance perspective, SCOC is indistinguishable from efficient flat crossbars. Computer simulations show that it competes well or even outperforms flat crossbars and hierarchical switches. We report data from our ASIC implementation at 32 nm of a SCOC 136×136 switch, with shallow buffers, connecting 25 Gb/s links. In this first incarnation, SCOC is used at the spines of a server-rack, fat-tree network. Internally, it runs at 9.9 Tb/s, thus offering a speedup of 1.45 ×, and provides a fall-through latency of just 61 ns.

SCOC: High-radix switches made of bufferless clos networks

Cost-efficient networks are critical in creating scalable large-scale systems, including those found in supercomputers and datacenters. High-radix routers reduce network cost by lowering the network diameter while providing a high bisection bandwidth and path diversity. However, as the port count increases, the high-radix router microarchitecture needs to scale efficiently. Hierarchical crossbar organization has been proposed where a single large crossbar is partitioned into many small crossbars and overcomes the limitations of conventional switch microarchitecture. Although the organization provides high performance, its scalability is limited due to power and area overheads by the wires and intermediate buffers. We propose alternative scalable router microarchitectures that leverage a network within the switch design of the high-radix routers themselves. These designs lower the wiring complexity and buffer requirements. For example, when a folded-Clos switch is used instead of the hierarchical crossbar switch for a radix-64 router, it provides up to 73%, 58%, and 87% reduction in area, energy-delay product, and energy-delay-area product, respectively. We also explore more efficient switch designs by exploiting the traffic-pattern characteristics of the global network and its impact on the local network design within the switch. In particular, we propose a bilateral butterfly switch organization that has fewer crossbars and half the number of global wires compared to the topology-agnostic folded-Clos switch while achieving better low-load latency and equivalent saturation throughput.

Network within a network approach to create a scalable high-radix router microarchitecture

DRAM is widely used as main-memory storage in contemporary computer systems. As VLSI process technology advances, more transistors can be integrated in a single die leading to higher storage capacity and communication throughput per DRAM chip. New DRAM standards are created in order to keep up with these trends, and many factors such as performance, energy efficiency, reliability, and fabrication/testing cost are considered when a new DRAM architecture is designed. However, there are few studies on DRAM array organizations that consider both performance and energy efficiency of entire computer systems using the organizations. In this paper, we explore the design space of contemporary DRAM array organizations by varying the number of pages that can be concurrently accessed and the size of the pages. We compare various mainmemory DRAM array organizations using multithreaded and multiprogrammed workloads on a chip-multiprocessor system with die-stacked DRAM memory in search of energy-efficient array configurations.

Exploring energy-efficient DRAM array organizations

As a critical part of a stored-program digital computer, the main memory system supports instructions and data to be consumed and produced by processing cores. High storage density and low manufacturing cost are the main design goals of the dynamic random access memory (DRAM) technology, making DRAM a primary option for main memory storage on contemporary computer systems that demand ever-increasing storage capacity. However, this focus on storage density and low cost leads to slow access time, low bandwidth, and high performance sensitivity on access patterns compared to the static random access memory (SRAM) technology, which is mainly used for on-chip storage. Thus, both the performance and energy efficiency of the main memory system are critical in improving the energy efficiency of the entire computer system. Also, emerging technologies such as 3D through-silicon vias and phase change memory have started to impact the structures and roles of main memory systems. This chapter categorizes and reviews recent research efforts to improve the performance or energy efficiency of contemporary memory systems. First, we describe conventional memory access scheduling policies which generate DRAM commands based on pending memory requests; we then review more advanced techniques that are focused on either improving performance or effectively managing DRAM power. Research works exploiting emerging technologies are introduced, and their impacts on future memory systems are analyzed. Then, we cover the proposals to modify memory modules or memory device architectures that reflect the access characteristics of future manycore systems.

Energy Awareness in Contemporary Memory Systems

A bidirectional, differential interface operating at 4Gb/s/link is presented. Self-diagnosis mode with on-chip BER measurement technique is implemented. The transceiver includes 4-tap Tx-FIR, and Rx linear equalizer of improved area efficiency and 25㏈ peak gain. Sampling timing at I/Os can be adjusted with 4ps resolution by the phase interpolation with multi-phase clocks. The 360˚ coverage of input sampling timing and controllable DC offset with the voltage twister enable the extraction of BER-based eye diagrams. This transceiver includes PRBS generation and verification blocks so that link performance can be monitored without external equipments. The test chip with two transceivers and clocking circuits occupies 1㎜ × 1㎜ and consumes 98.1mW from 1.2V supply.

A 4Gb/s/link Differential Bidirectional Serial Interface with Self-Diagnosis

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Papers

Network within a network approach to create a scalable high-radix router microarchitecture

Exploring energy-efficient DRAM array organizations

Energy Awareness in Contemporary Memory Systems

A 4Gb/s/link Differential Bidirectional Serial Interface with Self-Diagnosis