A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.

System and method for providing a configurable command sequence for a memory interface device

A method and apparatus for intelligent configuration register access on a PCI to PCI bridge ( 38 ) are provided. A read to configuration information of a connected PCI device ( 30 ) is identified. It is then determined whether the connected PCI device ( 30 ) is one for which the read should be trapped. If the read should not be trapped, the read is passed on to the connected PCI device ( 30 ). If the read should be trapped, the type of PCI device is determined for the connected PCI device ( 30 ). Data is then returned representing the configuration information in a format appropriate for the type of PCI device. In one aspect, the configuration information comprises the subsystem ID and subsystem vendor ID of the PCI device.

Method and apparatus for intelligent configuration register access on a PCI to PCI bridge

A controller (20 3) for coupling between a computer bus (20) and one or more units (22 1 , 22 2) compatible with the bus. The controller comprises a first input (28) for receiving a first reset signal issued from the computer bus, and a second input (30) for receiving a second reset signal. The controller further comprises circuitry (26) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry (24) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.

Circuits, systems, and methods for efficient wake up of peripheral component interconnect controller

Embodiments disclosed herein include operating the M-PHY communications over peripheral component interconnect (PCI)-based interfaces. Related cables, connectors, systems, and methods are also disclosed. In particular, embodiments disclosed herein take the M-PHY standard compliant signals and direct them through a PCI compliant connector (and optionally cable) so as to allow two M-PHY standard compliant devices having PCI connectors to communicate.

Operating m-phy based communications over peripheral component interconnect (pci)-based interfaces, and related cables, connectors, systems and methods

A method for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent functions are used for other purposes. Memory is configured to allow enumeration software to conclude that the non-existent functions do not in fact exist.

Method for extending the available number of configuration registers

A peripheral component interconnect (PCI) bridge which interfaces between PCI and local buses to provide a communicator for performing a communication between peripheral devices connected to the PCI bus and system devices connected to the local bus, is provided. The PCI bridge comprising a PCI register which is initialized according to a reset signal from the PCI bus and then stores configuration information on the PCI bus, a local register which is initialized according to a reset signal from the PCI bus and then stores configuration information on the local bus, PCI bus interface logic for performing interfacing according to the configuration information stored in the PCI register, local bus interface logic for performing interfacing according to the configuration information stored in the local register, and a logic transformer for reconstructing the PCI bus interface logic according to a command input from a user.

Programmable peripheral component interconnect (PCI) bridge for interfacing a PCI bus and a local bus having reconstructable interface logic circuit therein

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Programmable peripheral component interconnect (PCI) bridge for interfacing a PCI bus and a local bus having reconstructable interface logic circuit therein