Suehiro Sugitani
Nippon Telegraph and Telephone
68 Papers
540 Citations
Suehiro Sugitani is an academic researcher from Nippon Telegraph and Telephone. The author has contributed to research in topics: Monolithic microwave integrated circuit & Transistor. The author has an hindex of 15, co-authored 68 publications.
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Papers
Three-dimensional passive circuit technology for ultra-compact MMICs
H. Hirano,Kenjiro Nishikawa,Ichihiko Toyoda,Shinji Aoyama,Suehiro Sugitani,Kimiyoshi Yamasaki +5 more
TL;DR: In this paper, a 3D passive circuit for ultra-compact MMICs is proposed, which combines vertical passive elements, such as a wall-like microwire for shielding or coupling, and a pillar-like via connection with multilayer passive circuits.
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Photoluminescence characterization of InGaP/GaAs heterostructures grown by metalorganic chemical vapor deposition
TL;DR: In this article, the growth conditions of metalorganic chemical vapor deposition have been investigated for the purpose of obtaining abrupt InGaP/GaAs interfaces, and the photoluminescence (PL) spectra of QW quantum wells were used to characterize these interfaces.
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A compact V-band 3-D MMIC single-chip down-converter using photosensitive BCB dielectric film
Kenjiro Nishikawa,Suehiro Sugitani,Kenji Kamogawa,Tsuneo Tokumitsu,Ichihiko Toyoda,Masayoshi Tanaka +5 more
TL;DR: In this article, a 3D MMIC with flip-chip bonding is presented, which has a gain of 19.3 dB and an image rejection ratio of above 18 dB in the frequency range of 56.5-59.5 GHz.
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Three-dimensional MMIC technology for low-cost millimeter-wave MMICs
Kenjiro Nishikawa,Kenji Kamogawa,Belinda Piernas,Masami Tokumitsu,Suehiro Sugitani,Ichihiko Toyoda,Katsuhiko Araki +6 more
TL;DR: In this paper, the authors highlight the key advantages of 3D MMIC technology in the millimeter-wave frequency band and describe recently developed compact 3DMMICs on GaAs and Si substrates, which offer high integration levels, compactness, simple design procedures, and short fabrication turn-around time.
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Characterization of a thin Si‐implanted and rapid thermal annealed n‐GaAs layer
TL;DR: Very thin, high carrier concentration layers for high performance GaAs field effect transistors are realized by lamp annealing, combined with low energy (<30 keV) ion implantation.
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