Subarna Sinha
Stanford University
31 Papers
218 Citations
Subarna Sinha is an academic researcher from Stanford University. The author has contributed to research in topics: Logic synthesis & Sequential logic. The author has an hindex of 17, co-authored 31 publications. Previous affiliations of Subarna Sinha include Synopsys.
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Papers
Accurate process-hotspot detection using critical design rule extraction
Yen-Ting Yu,Ya-Chung Chan,Subarna Sinha,Iris Hui-Ru Jiang,Charles C. Chiang +4 more
- 03 Jun 2012
TL;DR: This paper proposes an accurate process-hotspot detection framework that extracts only critical design rules to express the topological features of hotspot patterns and adopts a two-stage filtering process to locate all hotspots accurately and efficiently.
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Using simulation and satisfiability to compute flexibilities in Boolean networks
Alan Mishchenko,Jin S. Zhang,Subarna Sinha,Jerry R. Burch,Robert K. Brayton,Malgorzata Chrzanowska-Jeske +5 more
TL;DR: This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) setsof candidate nodes for resubstitution.
Accurate detection for process-hotspots with vias and incomplete specification
Jingyu Xu,Subarna Sinha,Charles C. Chiang +2 more
- 05 Nov 2007
TL;DR: Theoretical results show that the proposed algorithm prevents the incorrect mis-match issues, while experimental results on fab provided process-hotspots show the algorithm is computationally efficient and practical for use on real industrial designs.
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Automating Logic Rectification by Approximate SPFDs
Yu-Shen Yang,Subarna Sinha,Andreas Veneris,Robert K. Brayton +3 more
- 23 Jan 2007
TL;DR: This paper first shows that a small set of predefined transformations may not allow rectification to exploit the full potential of the design, and proposes an automated simulation-based methodology to "approximate" sets of pairs of functions to be distinguished (SPFDs) and avoid the memory/time explosion problem.
The road to 3D EDA tool readiness
Charles C. Chiang,Subarna Sinha +1 more
- 19 Jan 2009
TL;DR: This paper identifies key stages in EDA that need modification to handle 3D ICs, highlight the challenges and review existing solutions, if they exist, and provides preferred features of the solutions necessary to enable3D IC design with the least amount of disruption.
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