MATRICs (Microwave Array Technology for Reconfigurable Integrated Circuits) is a DC-to-20 GHz general purpose reconfigurable array of RF circuits embedded in a flexible switch fabric. Fabricated in a commercial SiGe-on-SOI BiCMOS process, the MATRICs IC employs SiGe HBTs for high-linearity (> + 10 dBm IIP3) amplification and low phase-noise frequency generation, and SOI FETs for low-loss switching. It achieves high on-chip RF isolation (>80 dB at 16 GHz) due to the high-resistivity SOI substrate, differential signalling, and chip-scale flip-chip bump packaging. MATRICs will allow fixed-function RF systems to have the size, weight, and power benefits of a custom RF ASIC without the associated long development cycle and high NRE, and enable future RF subsystems to be dynamically reconfigured on-the-fly, adapting to changing environments.

The MATRICs RF-FPGA in 180nm SiGe-on-SOI BiCMOS

Heterogeneous and 3D Integration at DARPA

This paper overviews the Defense Advanced Research Projects Agency (DARPA) Adaptive RF Technologies (ART) and Arrays at Commercial Timescales (ACT) programs. These programs seek to create adaptable and reusable RF hardware in order to lower nonrecurring engineering development costs and timelines for RF systems and to allow RF hardware to be adapted to new missions after fielding. To achieve this vision, new RF architectures more amenable to reconfigurability have been developed along with component technologies that reduce the performance penalty associated with adaptive RF hardware.

/pdf/reconfigurable-electronics-for-adaptive-rf-systems-2q4lwd4o5p.pdf

Reconfigurable Electronics for Adaptive RF Systems

This article presents a dual-core quad-mode orthogonal-coupled wide frequency tuning range voltage-controlled oscillator (VCO) using mode control switches to realize the even/odd mode selection. Each core of the VCO adopts a parallel 8-shaped coil structure to avoid the influence of the other orthogonal-coupled one. Together with capacitor banks and varactors, the combination of orthogonal-coupled VCO cores demonstrates an extremely wide frequency tuning range on the basis of the existing range expanding from the dual-mode. The proposed VCO can be classified into two cases with different applications. One is that only one oscillation frequency is required; thus, four modes together show a wide frequency range. The other is that two different oscillation signals can be provided at the same time. The VCO has a measured tuning range of 8.3–21.7 GHz for the combination of low- and high-band cores. It consumes 4–6 mW with a measured phase noise of −127 dBc/Hz at a 10-MHz offset from a carrier of 9.6 GHz, and the FoM and FoMT are −179 and −199 dBc/Hz, respectively. The VCO is designed and implemented in the 65-nm complementary metal-oxide-semiconductor (CMOS) technology with a die area of 0.4 mm2. 

A Wide Tuning Range Dual-Core Quad-Mode Orthogonal-Coupled VCO With Concurrently Dual-Output Using Parallel 8-Shaped Resonator

A novel low-loss programmable microwave waveguide is demonstrated. The waveguide is developed for applications in field-programmable microwave circuits with similar levels of programmability as that seen in field-programmable gate arrays. The waveguide is realized with a field-programmable microwave substrate (FPMS). The substrate consists of small unit cells that can be individually reconfigured to have a range of positive dielectric constants or a negative dielectric constant. The substrate is contained in a metal parallel plate structure. Programming a positive material sandwiched between two negative material sidewalls results in a waveguide that behaves in a way that is described by the slab waveguide equations. Miniaturization and increased density of unit cells can result in lower loss and better performance. Two implementations of the FPMS are presented. One implementation is on FR4 using all industry standard processes and components. The other implementation uses low-temperature cofired ceramic and custom designed CMOS chips. The FR4 implementation is used to demonstrate programmable waveguides, amplifiers, and oscillators from 0.9 to 3 GHz. The LTCC implementation is used to demonstrate miniaturization of the FPMS. The proposed FPMS concept promises a new era of programmable microwave circuit design for cognitive radio, the Internet of things, and self-healing/adaptive systems.

/pdf/the-field-programmable-microwave-substrate-m0t04xj5gz.pdf

The Field-Programmable Microwave Substrate

A phase accumulator generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase and thus phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency.

Phase accumulator generating reference phase for phase coherent direct digital synthesis outputs

A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.

Modified delta-sigma modulator for phase coherent frequency synthesis applications

This paper presents a configurable frequency generator (CFG) capable of synthesizing frequencies between 10 MHz and 20 GHz with superior far-out phase noise of less than −150 dBc/Hz at 100 MHz offset when synthesizing >10 GHz, reference spurs less than −70 dBc, settling times of less 3 µs, and support for multiple reference frequencies through the use of a programmable bandwidth on-chip loop filter. The CFG is implemented in a 180nm SiGe-on-SOI BiCMOS process that enables high-frequency oscillation in the voltage-controlled oscillator (VCO), low parasitic switches for programmable passives, low phase noise HBTs, and excellent isolation between components sharing the same substrate.

20-GHz PLL-based configurable frequency generator in 180nm SiGe-on-SOI BiCMOS

A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.

Single-Level Parallel-Gated Carry/Majority Circuits And Systems Therefrom

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