The pseudo-MOS transistor (/spl Psi/-MOSFET) is a surprising and useful technique for the rapid evaluation of SOI wafers, prior to any CMOS processing. We review the static and dynamic modes of operation as well as the main models and methods for electrical parameter extraction. Selected numerical simulations are presented in order to clarify the optimal conditions of operation. Finally, practical applications are exemplified which illustrate the efficiency of the /spl Psi/-MOSFET technique for in situ characterization of SOI technologies and processes.

A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications

The first part of this paper deals with the standard etching techniques (Secco, Schimmel, Wright etch…) used for defects delineation in Si, SiGe, Ge and in new engineered substrates made from these starting materials, such as Silicon-on-Insulator (SOI), strained and extra-strained Silicon-on-Insulator (sSOI and XsSOI) and Ge-on-Insulator (GeOI). We focus in the second part on the new, chromium-free etching techniques which have recently been developed: chemical solutions containing other oxidizing agents (such as organic peracids, additional compounds such as bromine, iodine etc.) and gaseous HCl etching. We compare the performances of standard etching solutions with those of chromium-free etching techniques and list the specificities of the different techniques. Finally, we attempt to link defect etching results with those coming from physical characterization techniques (such as Raman spectroscopy, X-ray diffraction and Pseudo-MOSFET mobility measurements). A few similar studies can be found in the literature. Extensive work is however still necessary to establish a proper correlation between selective etching and those techniques. Up to now, defect selective etching techniques are the most sensitive ones for an accurate evaluation of crystalline quality.

Defect delineation and characterization in SiGe, Ge and other semiconductor-on-insulator structures

Radiation induced charge trapping versus Buried-Oxide (BOX) thickness on various Separation-by-IMplantation-of-OXygen (SIMOX) buried oxides has been determined. An inflection point has been observed in the voltage shift versus buried oxide thickness relationship. As such, the radiation-induced voltage shifts for thin buried-oxides are greater than what could be expected from a simple square-law relationship. However, for irradiation applied fields higher than that of typical buried-oxide fringing fields the thickness relationship obeys a square-law. These results can be explained by the location and magnitude of the radiation induced oxide charge centroid and its relationship to the BOX thickness. The location of the centroid for trapped positive charge is dependent on the radiation-induced hole mobility, which is related to SIMOX processing, as well as on geometry and charge saturation.

Charge trapping versus buried oxide thickness for SIMOX structures

Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction.

A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development

This work proposes a novel method for DNA detection by using the ψ-MOSFET configuration. Systematic measurements of the drain current vs. gate voltage revealed an important shift of the characteristics corresponding to the charge of the biochemical species attached to the top surface of the device. The results were validated by fluorescent scanning. The advantages of this method are its simplicity and sensitivity.

ψ-MOSFET Configuration for DNA Detection

A pseudo-metal/oxide/semiconductor transistor can be operated in situ in as-grown silicon on insulator materials. The measurement set-up and typical transistor characteristics are discussed. Methods are proposed to extract the basic parameters of minority and majority carriers, the buried oxide and SiSiO2 interface. The influence of the major experimental conditions is analyzed.

Point contact pseudo-metal/oxide/semiconductor transistor in as-grown silicon on insulator wafers

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Point contact pseudo-metal/oxide/semiconductor transistor in as-grown silicon on insulator wafers