다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

An obstacle to the use of graphene as an alternative to silicon electronics has been the absence of an energy gap between its conduction and valence bands, which makes it difficult to achieve low power dissipation in the OFF state We report a bipolar field-effect transistor that exploits the low density of states in graphene and its one-atomic-layer thickness Our prototype devices are graphene heterostructures with atomically thin boron nitride or molybdenum disulfide acting as a vertical transport barrier They exhibit room-temperature switching ratios of ≈50 and ≈10,000, respectively Such devices have potential for high-frequency operation and large-scale integration

http://repositorium.sdum.uminho.pt/bitstream/1822/21512/1/1112.4999_Science.pdf

Field-effect tunneling transistor based on vertical graphene heterostructures.

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

/pdf/device-scaling-limits-of-si-mosfets-and-their-application-299ftwsxth.pdf

Device scaling limits of Si MOSFETs and their application dependencies

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

/pdf/low-voltage-tunnel-transistors-for-beyond-cmos-logic-3w5c8knrc5.pdf

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

This work presents a thorough study of quasi-ballistic transport in DGSOI MOSFETs at very low drain-to-source bias. The simulations performed with a Quantum corrected Ensemble Monte Carlo simulator (Q-EMC) show contrasting trends in the nanoballisticity at moderate and low lateral field. For each regime, the mechanisms governing the quasi-ballistic transport are analyzed. The ratio between transit time and relaxation time explains why the proportion of ballistic carriers increases with drain bias until VD ap kT/q.

Ballisticity at very low drain bias in DG SOI Nano-MOSFETs

Effective Capacitance Area for Pseudo-MOSFET Characterization of Bare SOI Wafers by Split-C(V) Measurements

In parallel to presentations documenting the performance of state-of-the-art FDSOI CMOS devices, we discuss selected physical mechanisms and emerging device architectures enabled by FDSOI technology.

FDSOI devices: Issues and innovative solutions

Demonstration of A2RAM memory cells fabricated by ion implantation.

Z2-FET based ESD protections: innovative local clamps for UTBB FD-SOI Technology.

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