A survey of hardware Trojan threat and defense

There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both application-specified integrated circuits and field-programmable gate arrays. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1) the area and power costs of our approach can range between 7.4%–165% and 7%–60%, respectively, depending on the design and the attacks targeted; 2) the speed impact can be minimal (close to 0%); 3) our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4) our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse engineering); and 5) our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly.

pdf/tpad-hardware-trojan-prevention-and-detection-for-trusted-1g7httlh67.pdf

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Conventional and machine learning approaches as countermeasures against hardware trojan attacks

Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.

https://www.mdpi.com/1424-8220/20/18/5165/pdf

Hardware Trojans in Chips: A Survey for Detection and Prevention.

Terahertz radiation for inspection and fault detection has been of interest for the semiconductor industry since the first generation and detection of THz signals. Until recent hardware advances, THz systems lacked the signal quality and reliability for use as an effective nondestructive testing (NDT) method. Incremental advances in THz sources, detectors, and signal processing resulted in the successful applied-industrial use of THz NDT techniques on carbon fiber laminates, automotive coatings, and for detection of counterfeit pharmaceutical tablets. Semiconductor inspection and verification methods ensure the functionality and thereby safety of vital electronics for several critical industries. For this reason, the reliability and verification of a THz NDT method must exceed currently used inspection systems. With recent laboratory access to THz radiation, THz inspection methods are often compared with existing optical, electrical, and volumetric semiconductor verification techniques for their production monitoring and failure analysis viability. This review will cover THz techniques and their applications at the printed circuit board (PCB), integrated circuit (IC), and transistor/gate scales. The THz radiation gap spans between optical and electronic ranges with a millimeter-sized wavelength allowing for adequate penetration of plastic and ceramic and semiconductor materials. THz radiation can be used to determine structural features, electrical signatures in the THz range, and chemical information simultaneously. Cost and environmental limitations restricted the ability for THz NDT semiconductor inspection methods to escape the lab and succeed in the dynamic environment of a semiconductor fabrication environment. Hybridized metrology methods incorporating information from multiple inspection tools are a regime where THz spectral and structural data can be combined with existing methods such as optical, x-ray, or E-beam. THz can be used initially to offer support to the complex failure analysis and verification requirements of the semiconductor industry from nanoscale to macroscale features and components. For THz systems to become independent inspection tools used for semiconductor production monitoring, in the lab or fab, this will require a confident level of statistical process control for THz signal generation, detection, or processing. Applied industrial semiconductor device inspection will likely be a result of a combination of research into THz hardware, reconstruction techniques, and the widespread application of machine learning techniques. Many breakthroughs occurred over the years to enable successful nondestructive characterization and inspection of semiconductor devices from the nanoscale transistors to fully packaged integrated circuits and assembled PCBs.

https://www.spiedigitallibrary.org/journals/optical-engineering/volume-60/issue-6/060901/Review-of-THz-based-semiconductor-assurance/10.1117/1.OE.60.6.060901.pdf

Review of THz-based semiconductor assurance

Long ago, the story goes, Greek soldiers tried for 10 years to conquer the city of Troy Eventually, they departed, leaving behind a large wooden horse, apparently as a gift The Trojans pulled the beautiful tribute inside Later, a group of Greek soldiers slipped out of the horse and opened the gates for their compatriots, who easily sacked the sleeping city

The Trojan-proof chip

We show, for the first time, a BEOL carbon nanotube FET (CNFET) + Resistive RAM (RRAM) stack through monolithic 3D (M3D) integration, directly over silicon (Si) CMOS, that achieves comparable performance (read power write energy/latency, endurance, retention, multiple bits-per-cell capability) in the same footprint as conventional RRAM stack using FEOL Si FET access transistors. This process is established within SkyWater Technology Foundry (90/130nm technology node on 200mm Si wafers), and an apples-to-apples comparison is made versus FEOL Si FET+RRAM fabricated on the same wafers, from the same foundry, at the same node. Such BEOL CNFET+RRAM technology unlocks a large architecture design space with significant system-level energy-delay product (EDP) benefits vs. FEOL Si+RRAM-only designs, e.g., $\gt 5 \times $ EDP benefits for new iso-footprint, iso-memory-capacity M3D architectures uniquely enabled by our M3D physical design. Our BEOL CNFET+RRAM therefore creates a new and complementary integration path for dramatically improving system-level energy and delay, iso-node and iso-footprint. 

Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM

We present 1-FeFET-1-RRAM (1F1R) hybrid nonvolatile memory for dense embedded memory application. By allocating 2 bits each in the RRAM and FeFET, we show 4 bits/cell capability with retention over 104 seconds at 85 °C. An array of 1F1R cells enables a new compute-in-memory (CIM) concept – Masked CIM. Masked CIM can store 2× the amount of signed weights compared with traditional CIM array. Doubling synapses density allows implementing larger neural network models that is critical for applications beyond toy datasets such as MNIST or CIFAR-10.

4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory

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The Trojan-proof chip

Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM

4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory