Advanced Mathematical Methods for Scientists and Engineers

Frequency-modulated continuous-wave (FMCW) radars with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems, the spot phase noise of the chirp generator is converted to the intermediate frequency of the receiver making it difficult to detect two close targets, while spurs cause the detection of false targets. For those reasons, medium-range radar applications in the 77-to-81GHz band typically specify spot phase noise lower than −90dBc/Hz at 1MHz offset and spur level below −50dBc. Unlike triangular chirps, saw-tooth chirps allow for a reduced dead time for range detection. However, any practical modulator needs a finite time (idle time) to make a large frequency jump at the end of the saw-tooth, and this limits the duty cycle of the saw-tooth. For instance, a fast saw-tooth chirp with 200kHz rate and 95% duty cycle leaves the idle time of only 250ns. Fractional-N PLLs can be used as chirp modulators. Unfortunately, low phase noise and spur levels require a narrow PLL bandwidth, while short idle time demands for a wide one. The two-point injection of the modulation signal, both from the modulus control of the divider and the tuning input of the voltage-controlled oscillator (VCO), is a known method to simultaneously achieve a narrow PLL bandwidth and fast modulation. However, even in that scheme, a frequency modulation error is mainly limited by gain mismatch between the two injection paths and by the linearity of the VCO [2]. In this work, a 20-to-24GHz digital bang-bang PLL, which uses the two-point modulation scheme to generate triangular and saw-tooth chirp signals, is presented. Unlike previous works [1-4], this architecture is able to generate fast saw-tooth chirps with the slope up to 173MHz/js, the idle time below 200ns, and the rms frequency error of better than 0.06%. The gain mismatch between the two modulation paths are automatically calibrated by a digital algorithm [5], and the input of the digitally controlled oscillator (DCO) is pre-distorted via an automatic background correction scheme, which compensates for the DCO nonlinearity.

/pdf/a-23-ghz-low-phase-noise-digital-bang-bang-pll-for-fast-5c2ye7krpb.pdf

A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign–sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm2. The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved.

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

To obtain a 20cm-resolution image within a 15m distance using an X-band FMCW radar, an agile chirp frequency synthesizer phase-locked loop (FSPLL) with a wide chirp bandwidth (BW) greater than 750MHz and a short chirp period (Tm) less than 100µs is necessary. Challenges arise as one tries to realize a triangular chirp profile in Fig. 13.1.1 with a fast chirp slope (=BW/Tm) and precise linearity. In particular, many FMCW FSPLLs exhibit increased frequency errors around the turn-around points (TAPs), degrading the effective resolution achievable. For instance, for FSPLLs modulating either the reference or feedback clock frequency [1–3], the finite loop bandwidth of the PLL limits the maximum chirp slope as well as the linearity of the chirp profile. Moreover, many of these PLLs use a multi-modulus frequency divider (FD) and delta-sigma modulation (DSM) [2], which put further constraints on the maximum PLL bandwidth to filter the quantization noise. While a two-point modulation (TPM) scheme can decouple the conflicting requirements on the PLL bandwidth [4–6], the gain or timing mismatch between the two modulation paths and limited resolution of the DSM-based FD can still limit the chirp linearity, especially when one tries to push the chirp slope faster.

13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications

This paper presents a fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A $\Delta \Sigma $ -less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm2 and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

A 92 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter The analysis on the loop dynamics and design of the optimal loop filter are presented As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 12 ps rms integrated jitter at 92 GHz and 158 μs settling time with 700 kHz bandwidth while dissipating 639 mW at a 12 V nominal supply

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLL's second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs the proposed PLL implements the peaking-free loop filter directly in digital domain without requiring additional components. A time-to-digital converter (TDC) is implemented as a set of three binary phase-frequency detectors that oversample the timing error with time-varying offsets achieving a linear TDC gain and PLL bandwidth insensitive to the jitter condition. And a 9.2-GHz digitally-controlled LC oscillator (DCO) with transformer-based tuning realizes a predictable DCO gain set by a ratio between two digitally-controlled currents. The prototype 9.2-GHz-output digital PLL fabricated in a 65nm CMOS demonstrates a fast settling time of 1.58-μs with 690-kHz bandwidth. The PLL has a 3.477-psrms divided clock jitter and -120dBc/Hz phase noise at 10MHz offset while dissipating 63.9-mW at a 1.2-V supply.

A 9.2-GHz digital phase-locked loop with peaking-free transfer function

An all-digital DLL with 2-cycle lock time and 47-mUIpp jitter without dithering is presented. Implemented in 65nm CMOS, the DLL consumes only 1.3-mW at 1.6-GHz and occupies 0.016-mm2, making it suitable for low-cost clock deskewing and data alignment circuits in large-scale 3D ICs. A set of custom-designed, serially-connected control registers whose propagation delay is matched to that of the delay stages acquires the initial lock setting by propagating a set signal for a duration equal to the delay error. Subsequently, an adaptive phase-interval detector (APID) that finds the delay interval enclosing the optimal delay value with a minimal number of samples keeps the DLL in lock without causing dithering or sacrificing bandwidth.

A 1.3-mW, 1.6-GHz digital delay-locked loop with two-cycle locking time and dither-free tracking

A 2 $\times $ blind-oversampling, fractionally spaced equalizer (FSE) receiver is presented as an effective way to combine adaptive equalization and timing recovery in a single control loop. To additionally support plesiochronous clocking, the presented work realizes an infinite-range timing recovery using a set of two four-tap FSEs with a 0.5-UI timing offset, only one of which is selected to recover the data. The selection seamlessly alternates between the two, each time a 0.5-UI timing drift occurs. The optimal time to switch the selection is detected by observing the currently adapted FSE tap coefficients and its main cursor position. An equivalent timing recovery loop model is derived. A current-integrating summer and multi-input regenerative latch help the four-tap FSEs and four-tap decision-feedback equalizers (DFEs) achieve low-power dissipation, respectively. A prototype receiver fabricated in a 28-nm CMOS consumes 3.5 pJ/bit and 0.10 mm2 at 9 Gb/s while compensating for a 22-dB channel loss and 100-ppm frequency offset between the transmitted data and blind sampling clocks.

A 2 $\times$ Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery

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