This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used smoothing functions for the effective drain-source voltage (Vds,eff ). The proposed model not only builds in physically all the terminal-bias variations, but is also extended to include source/drain asymmetry in real devices in a single-core compact model. The new model resolves a key bottleneck in existing models for passing the Gummel symmetry test (GST) in higher order derivatives, which has to be traded off for the geometry-dependent Vds,eff smoothing parameter. The complete drain-current model, including the effects of velocity saturation and overshoot as well as source/drain series resistance, has also been reformulated with the same ldquobulk-referencingrdquo concept. It is shown that the proposed model passes the GST in all higher order derivatives without any constraint on the value of the smoothing parameter. It also demonstrates potential extension to modeling asymmetric MOSFETs, which is becoming an important model capability.

A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

This paper reviews the development of the MOSFET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI, double-gate (DG) FinFETs and gate-all-around (GAA) silicon-nanowires (SiNWs), based on the unified regional modeling (URM) approach. The complete scaling of body doping and thickness with seamless transitions from one structure to another is achieved with the unified regional surface potential, in which other effects (such as those due to poly-gate doping and quantum-mechanical) can be incorporated. The unique features of the Xsim model and the essence of the URM approach are described.

Unification of MOS compact models with the unified regional modeling approach

This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gateall-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The core Xsim model is extended from the bulk-MOS model that encompasses partialand full-depletion SOI as well as DG/GAA FinFET/SiNW devices, with doping scaling from highly-doped to undoped body. Terminal currents and terminal charges are physically scalable over wide ranges of geometry and structural variations, satisfying the basic model benchmark tests such as Gummel symmetry test (GST), slope-ratio test (SRT), tree-top test (TTT), harmonic-balance test (HBT), as well as transcapacitance symmetry and reciprocity. The ultimate goal of the Xsim model is for unification of MOSFET compact models with various gate, body, as well as source/drain structures and dimensions in one unified core framework for simulating and designing integrated circuits in future generation technologies, including bulk/SOI/FinFET/SiNW or a hybrid of them.

/pdf/xsim-benchmark-tests-for-the-unified-dg-gaa-mosfet-compact-3vt58at0t2.pdf

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

A new approach to modeling non-classical CMOS devices, such as strainedsilicon (s-Si) and double-gate (DG) MOSFETs, is presented. We have employed a unified regional, non-pinned surface-potential based modeling approach, which is consistent with the prior development for bulk-MOS formulations. The key idea is to develop unified models with the correct physics and boundary conditions built into them, so that there is a seamless transition of models among different device structures like bulk, DG, SOI, and strained silicon. Threshold-voltage models are derived for surfaceand buried-channel strained-silicon MOSFETs based on the 1-D Poisson equation. A unified regional modeling (URM) approach has been used to develop a single-piece physics-based charge model. An implicit iterative technique to calculate surface potential and charge was developed using the URM solutions. The model is generic and can be applied to all hetero-structure devices. With the structural and band information, the model can predict the threshold voltage, surface potential, charge and capacitance in surfaceand buried-channel strained-silicon MOSFETs. A doping dependant shift in the plateau of a strained-silicon MOSFET C-V curve was observed. The physics behind this behavior was studied and modeled physically. A study on the different mobility models for strained-silicon MOSFETs has been carried out. Multiple-gate structures, such as double gate, Q gate, n gate and surrounding gate, are gaining a lot of attention due to their excellent sub-threshold characteristics and scalability. DG MOSFETs can be classified into symmetric and asymmetric MOSFETs based on the structure and bias applied at the two gates. When doping is included in the modeling of multiple-gate structures, the field equation is not integrable. We have used XVI ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library

/pdf/nanoscale-strained-si-sige-and-double-gate-mosfet-modeling-45f9bhfi7z.pdf

Nanoscale strained-Si/SiGe and double-gate MOSFET modeling

/pdf/compact-modeling-of-gate-all-around-silicon-nanowire-mosfets-1rxsy56j44.pdf

Compact modeling of gate-all-around silicon nanowire mosfets.

/pdf/unified-ac-charge-and-dc-current-modeling-for-very-deep-2ngfj2bise.pdf

Unified AC charge and DC current modeling for very-deep-submicron CMOS technology

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Unified AC charge and DC current modeling for very-deep-submicron CMOS technology