Shreepad Panth
Georgia Institute of Technology
33 Papers
385 Citations
Shreepad Panth is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Three-dimensional integrated circuit & Integrated circuit. The author has an hindex of 18, co-authored 33 publications. Previous affiliations of Shreepad Panth include Intel & Qualcomm.
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Papers
3D-MAPS: 3D Massively parallel processor with stacked memory
Dae Hyun Kim,Krit Athikulwongse,Michael B. Healy,Mohammad M. Hossain,Moongon Jung,Ilya Khorosh,Gokul Kumar,Young-Joon Lee,Dean L. Lewis,Tzu-Wei Lin,Chang Liu,Shreepad Panth,Mohit Pathak,Minzhen Ren,Guanhao Shen,Taigon Song,Dong Hyuk Woo,Xin Zhao,Joungho Kim,Ho Choi,Gabriel H. Loh,Hsien-Hsin Lee,Sung Kyu Lim +22 more
- 03 Apr 2012
TL;DR: 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM.
187
Design and CAD methodologies for low power gate-level monolithic 3D ICs
Shreepad Panth,Kambiz Samadi,Yang Du,Sung Kyu Lim +3 more
- 11 Aug 2014
TL;DR: This paper develops, for the first time, a complete RTL-to-GDSII design flow for gate-level M3D, and uses this flow along with a 28nm PDK to build layouts for the OpenSPARC T2 core.
121
Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs
TL;DR: This paper uses the OpenSPARC T2 SoC as a case study, implements it in a 28-nm fully depleted silicon on insulator foundry process, and demonstrates that it can achieve up to 12% and 8% power savings for a single block and SoC, respectively, when compared with their 2-D counterparts implemented using commercial tools.
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Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)
Dae Hyun Kim,Krit Athikulwongse,Michael B. Healy,Mohammad M. Hossain,Moongon Jung,Ilya Khorosh,Gokul Kumar,Young-Joon Lee,Dean L. Lewis,Tzu-Wei Lin,Chang Liu,Shreepad Panth,Mohit Pathak,Minzhen Ren,Guanhao Shen,Taigon Song,Dong Hyuk Woo,Xin Zhao,Joungho Kim,Ho Choi,Gabriel H. Loh,Hsien-Hsin S. Lee,Sung Kyu Lim +22 more
TL;DR: The architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology are described.
67
Patent
3d floorplanning using 2d and 3d blocks
Kambiz Samadi,Shreepad Panth,Yang Du +2 more
- 11 Mar 2013
TL;DR: In this article, the authors present a methodology for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies.
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